Selective Barrier Layer for Copper LCD Transistors
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Solution Overview
Problem
The use of copper electrodes in LCD manufacturing leads to issues such as poor adhesion with dielectric layers, high diffusion coefficients, and reactions with silicon, causing degradation in electrical performance, which are exacerbated by the need for a barrier layer that increases resistance and is difficult to control due to lithographic and etching processes.
Innovation Solution
A selective electroless plating process is used to form a barrier layer only on the semiconductor layer, eliminating the need for additional masks and reducing unnecessary resistance by ensuring the barrier layer is uniformly deposited only where needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is formed using conventional lithographic and etching processes, then copper diffusion is prevented, but resistance increases and manufacturing precision deteriorates
Solution Approach 1:
The patent replaces mechanical lithographic and etching processes with a chemical self-assembly approach. The barrier layer material spontaneously assembles at the interface between the copper electrode and semiconductor layer through chemical affinity, eliminating the need for mask-based lithography and etching. This chemical self-assembly mechanism provides superior placement precision while preventing copper diffusion.
Solution Approach 2:
The barrier layer formation process is self-directed through chemical affinity between the barrier material and the copper-semiconductor interface. The system automatically forms the barrier layer exactly where needed without external guidance from masks or etching patterns, enabling self-positioning with high precision and eliminating unnecessary barrier layers in non-critical regions.
2Reliability
If a barrier layer is formed using conventional deposition and etching, then copper diffusion is prevented, but device complexity increases
Solution Approach 1:
The patent combines multiple sequential processes (deposition, lithography, etching) into a single self-assembly step. The barrier layer forms in situ at the copper-semiconductor interface through chemical affinity, merging the functions of deposition and pattern formation into one operation. This reduces the total number of process steps and simplifies the manufacturing sequence.
Solution Approach 2:
The patent extracts and eliminates the lithography and etching steps from the conventional barrier layer formation process. By using chemical self-assembly, only the essential barrier layer deposition remains, removing unnecessary intermediate steps and reducing overall process complexity while maintaining diffusion prevention functionality.
3Productivity
If copper is used as conductive material, then circuit density and imaging quality improve, but adhesion and diffusion control deteriorate
Solution Approach 1:
The patent introduces a barrier layer as an intermediary substance between the copper electrode and semiconductor layer. This intermediate layer has specific chemical affinity for both copper and the semiconductor material, creating a stable interface that prevents direct copper-semiconductor contact. The barrier layer mediates the interaction between copper and semiconductor, preventing diffusion while maintaining electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents improper resistance increases and copper diffusion, maintaining the electrical performance of the transistor while allowing precise control over conductor width by eliminating the dual-layer structure and undercutting issues.
Implementation Method 1
an electroless plating procedure is performed to selectively form a barrier layer that only wraps a semiconductor layer
Data Source
AI summary
A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.