Selective Bit Line Clamping for SRAM In-Memory Compute
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Solution Overview
Problem
In-memory computation circuits using SRAM arrays face the risk of unwanted data flips during simultaneous row access, which compromises the accuracy of computational operations due to excessive bit line voltage drops.
Innovation Solution
Implementing a selective bit line clamping mechanism that senses voltage levels on bit lines and activates a voltage clamp circuit to maintain the voltage above a threshold level, preventing further drops and thus preventing data flips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous access to multiple rows of SRAM array is performed for in-memory compute operation, then computational throughput is improved, but bit line voltage drops excessively causing data flips
Solution Approach 1:
The patent applies preliminary anti-action by detecting the voltage level on bit lines before data flips can occur and activating the clamping circuit proactively. The detection circuit monitors bit line voltage and triggers the clamp signal to prevent excessive voltage drops that would cause data flips, thus counteracting the harmful effect before it compromises data integrity while maintaining simultaneous row access for high throughput.
2Reliability
If bit line voltage is clamped to prevent data flips, then data integrity is improved, but circuit complexity increases
Solution Approach 1:
The patent introduces an intermediary detection circuit that sits between the bit line and the clamping mechanism. This detection circuit monitors bit line voltage levels and generates clamp signals only when necessary, acting as a mediator that enables the clamping function without requiring constant activation. This approach maintains data integrity while minimizing the impact on circuit complexity by enabling selective rather than continuous clamping operation.
Data Source
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AI summary
A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.