Selective Bit Line Precharge for Digital Memory Power Reduction
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Solution Overview
Problem
Current digital memory architectures consume excessive power due to the need to precharge all bit lines before each access cycle, which is inefficient, especially when only a subset of bit lines are accessed, and result in increased latency and power consumption, particularly in mobile and communication applications where random access is required.
Innovation Solution
The solution involves selectively precharging only the subset of bit lines needed for access, allowing the precharge and access cycles to occur simultaneously, and enabling only necessary sense amplifiers to conserve power and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all bit lines are precharged before each access cycle, then the memory is ready for any random access, but power consumption increases and latency increases
Solution Approach 1:
The memory bank is divided into multiple segments or portions, allowing selective precharging of only the specific segment that contains the target bit line, rather than precharging all bit lines in the entire bank. This segmentation enables localized operations that reduce power consumption while maintaining random access capability.
Solution Approach 2:
The precharge operation is applied locally only to the specific bit line or small group of bit lines that are about to be accessed, rather than uniformly to all bit lines. This local quality approach ensures that power and time resources are concentrated only where needed, reducing overall power consumption and latency.
2Adaptability or versatility
If all bit lines are precharged before each access cycle, then the memory is ready for any random access, but access latency increases
Solution Approach 1:
The memory bank is divided into multiple segments or portions, allowing selective precharging of only the specific segment that contains the target bit line, rather than precharging all bit lines in the entire bank. This segmentation enables localized operations that reduce power consumption while maintaining random access capability.
Solution Approach 2:
The precharge operation is performed in advance but only on the specific bit line or small group of bit lines that are about to be accessed, rather than uniformly to all bit lines. This preliminary action ensures that the necessary bit lines are ready before access while avoiding unnecessary precharging of other bit lines, thus reducing access latency.
3Adaptability or versatility
If the entire bank is precharged before accessing a small number of bits, then all bits are accessible, but power consumption and temperature increase
Solution Approach 1:
The memory bank is divided into multiple segments or portions, allowing selective precharging of only the specific segment that contains the target bit line, rather than precharging all bit lines in the entire bank. This segmentation enables localized operations that reduce power consumption while maintaining random access capability.
Solution Approach 2:
Instead of performing a full bank precharge, only a partial precharge of the necessary bit lines or small segments is performed. This partial action is sufficient to enable the required access while avoiding the excessive power consumption and temperature increase associated with precharging the entire bank.
Data Source
Figure 1(a)~1(h)
Figure 2A~2C
Figure 3
AI summary
Methods, apparatuses and systems of operating digital memory where the digital memory device (figure 7) including a plurality of memory cells (figure 6) receives a command to perform an operation on a subset of memory cells, where the subset of memory cells contains fewer memory cells than the device as a whole and where the device selectively precharges, in response to the received command, only a subset of bit lines associated with the subset of memory cells (figure 4).