Selective Bit-Line Sensing for SRAM Energy Reduction
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Solution Overview
Problem
Conventional SRAM memory architectures face high energy consumption due to simultaneous activation of numerous memory cells during inference operations in neural networks, leading to increased energy consumption and inefficiency.
Innovation Solution
A selective bit-line sensing method that determines whether to sense bit-lines or complementary bit-lines based on the asymmetric distribution of 0's and 1's in neuron weights, allowing for the activation of either first or second word-lines, thereby reducing accumulated current during sensing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional SRAM memory architecture is used with fixed sensing operation, then the memory cell design is simple, but energy consumption is high due to simultaneous activation of numerous memory cells
Solution Approach 1:
The patent implements dynamic sensing operation that adapts to the distribution characteristics of neuron weights. The sensing operation transitions from a fixed conventional approach to a dynamic approach that selectively activates bit-lines or complementary bit-lines based on real-time analysis of weight distribution (number of 0's vs 1's), thereby optimizing energy consumption while maintaining correctness
Solution Approach 2:
The patent changes the sensing parameter selection based on the distribution parameter of stored data. By analyzing the number of 0's and 1's in neuron weights, the system dynamically selects which bit-lines to sense, transforming the fixed sensing approach into an adaptive one that optimizes energy consumption according to data characteristics
2Productivity
If all word lines are activated during inference operation, then complete neural network computation is achieved, but accumulated current increases significantly
Solution Approach 1:
The patent extracts only the necessary sensing operations from the complete set of bit-line sensing operations. By analyzing neuron weight distribution, it identifies and executes only the essential sensing operations (selecting which bit-lines or complementary bit-lines to sense), thereby reducing accumulated current while maintaining complete neural network computation capability
Solution Approach 2:
Instead of sensing all bit-lines during inference operations, the patent applies partial action by selectively sensing only the necessary bit-lines or complementary bit-lines based on weight distribution analysis. This partial sensing approach reduces accumulated current while still achieving complete neural network computation through the selective sensing strategy
3Measurement precision
If differential sensing operation is used with both bit-lines, then sensing accuracy is improved, but energy consumption increases due to sensing both BL and BLB
Solution Approach 1:
The patent applies local quality by making the sensing operation asymmetric based on local data characteristics. Instead of uniformly sensing both bit-lines BL and BLB across all operations, it locally adapts the sensing approach by selecting which bit-line to sense based on the specific distribution of 0's and 1's in the neuron weights, thereby optimizing both accuracy and energy consumption
Solution Approach 2:
The patent implements asymmetry in the sensing operation by treating bit-lines BL and complementary bit-lines BLB differently based on the distribution characteristics of stored data. When the number of 0's exceeds the number of 1's, one sensing approach is selected; when 1's exceed 0's, the alternative approach is selected. This asymmetric sensing strategy maintains sensing accuracy while reducing energy consumption compared to symmetric differential sensing of both bit-lines
Data Source
AI summary
A selective bit-line sensing method is provided. The selective bit-line sensing method includes the steps of: generating a neuron weights information, the neuron weights information defines a distribution of 0's and 1's storing in the plurality of memory cells of the memory array; and selectively determining either the plurality of bit-lines or the plurality of complementary bit-lines to be sensed in a sensing operation according to the neuron weights information. When the plurality of bit-lines are determined to be sensed, the plurality of first word-lines are activated by the artificial neural network system through the selective bit-line detection circuit, and when the plurality of complementary bit-lines are determined to be sensed, the plurality of second word-lines are activated by the artificial neural network system.