Selective Bitline Precharging in NAND Flash Memory
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Solution Overview
Problem
Current flash memory devices are slower and consume more power due to inefficient bitline charging methods, which hinder the speed and efficiency of data operations in non-volatile memory systems.
Innovation Solution
The implementation of a selective bitline precharge circuit that precharges only the bitlines that require it, reducing unnecessary power consumption and enhancing data sensing operations by using a precharge compensation scheme to minimize charge leakage and optimize bitline charging times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bitlines are precharged globally during every sense operation, then data sensing reliability is improved, but power consumption increases
Solution Approach 1:
The bitline precharging operation is segmented from global to selective. Instead of precharging all bitlines simultaneously, the circuit identifies and precharges only specific bitlines that require it based on program inhibit signals. This segmentation reduces the number of bitlines subjected to precharge current, thereby lowering overall power consumption while maintaining sensing reliability for the necessary bitlines.
Solution Approach 2:
The invention applies partial precharging action by precharging only a subset of bitlines rather than all bitlines. The selective precharge circuit activates precharging for individual bitlines based on program inhibit signals, performing exactly the necessary precharge operations without excessive precharging of bitlines that don't require it, thus optimizing power consumption.
2Measurement precision
If bitline precharging is performed for all bitlines, then data sensing accuracy is improved, but operation speed decreases
Solution Approach 1:
The selective precharge circuit segments the bitline precharging process to target only specific bitlines that require precharging. By dividing the bitline set into groups needing precharge and groups not needing precharge, the circuit eliminates unnecessary precharging operations, thereby reducing overall operation time and improving speed while maintaining sensing accuracy for the bitlines that require it.
Solution Approach 2:
The invention skips unnecessary precharging operations for bitlines that do not require precharging. By identifying bitlines that can be skipped in the precharge sequence based on program inhibit signals, the circuit rushes through the precharge process more efficiently, reducing total operation time while ensuring accurate sensing for bitlines that do require precharging.
3Use of energy by moving object
If selective bitline precharging is implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The selective precharge circuit introduces intermediary control elements (program inhibit signals and control logic) that mediate between the global precharge command and individual bitline precharge operations. These intermediaries enable selective activation of precharging only where needed, reducing power consumption while the added complexity is confined to the control logic rather than the entire memory structure.
4Reliability
If global bitline precharging is used, then data sensing reliability is maintained, but operation time increases
Solution Approach 1:
The selective precharge circuit performs partial precharging action by activating precharging only for bitlines that require it, as indicated by program inhibit signals. This partial action approach maintains sensing reliability for the necessary bitlines while eliminating time-wasting precharge operations on bitlines that don't need precharging, thereby reducing overall operation time.
Data Source
AI summary
A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.