Selective Cache Flushing for Memory-Centric Operations
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Solution Overview
Problem
Existing solutions for supporting memory-centric operations on processor-side cached data are inefficient, as they either consume significant resources or fail to provide the necessary data availability for memory-centric computations, particularly when operations span beyond the coherence domain.
Innovation Solution
Implementing a novel write back functionality that selectively flushes dirty cached data to the completion level of memory-centric operations, ensuring data availability while maintaining coherence and avoiding unnecessary flushing, thereby allowing cores to perform memory-centric operations on cached data without compromising cache benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processor-side caches are flushed to memory to support memory-centric operations, then data availability for memory-centric operations is improved, but computational and storage resources are consumed excessively
Solution Approach 1:
The patent applies local quality by making the cache flushing operation selective rather than universal. The cache controller identifies and flushes only the specific dirty cached data blocks that are needed for upcoming memory-centric operations, rather than flushing all cached data. This selective approach ensures data availability where needed while avoiding unnecessary computational and storage resource consumption for data that will not be used by memory-centric operations.
2Reliability
If all cached data is flushed to main memory, then data availability for memory-centric operations is ensured, but storage resources are wasted when data is flushed beyond the completion level
Solution Approach 1:
The patent applies segmentation by dividing the memory hierarchy into distinct levels (processor-side caches, memory-side caches, and main memory) and flushing data only to the necessary completion level. The cache controller determines the appropriate completion level for each memory-centric operation and flushes dirty cached data only to that specific level, not all the way to main memory. This segmented approach ensures data availability at the required level while preventing storage resource waste by avoiding unnecessary flushing to lower levels of the memory hierarchy.
3Loss of energy
If processor-side caches are not flushed, then resource consumption is reduced, but data integrity for memory-centric operations cannot be guaranteed
Solution Approach 1:
The patent applies preliminary action by proactively identifying which dirty cached data blocks will be needed for upcoming memory-centric operations and flushing them before the operations execute. The cache controller predicts or determines the data requirements of memory-centric operations in advance, initiates the selective flushing of relevant dirty cached data to appropriate completion levels, and ensures data integrity is established before the memory-centric operations begin. This preliminary action prevents data integrity issues while avoiding the resource consumption of flushing all cached data.
4Reliability
If both memory and memory-side caches are included in the coherence domain, then data consistency is maintained, but protocol complexity increases greatly
Solution Approach 1:
The patent applies the taking out principle by extracting memory-side caches from the processor-side coherence domain while maintaining data consistency through a different mechanism. Instead of including memory-side caches in the traditional processor coherence domain (which would require complex protocol extensions), the patent implements a separate coherence protocol for memory-side caches that works in conjunction with the processor coherence protocol. This extraction approach maintains data consistency across the entire system while avoiding the need to greatly increase the complexity of the original processor coherence protocol.
Data Source
AI summary
A technical solution to the technical problem of how to support memory-centric operations on cached data uses a novel memory-centric memory operation that invokes write back functionality on cache controllers and memory controllers. The write back functionality enforces selective flushing of dirty, i.e., modified, cached data that is needed for memory-centric memory operations from caches to the completion level of the memory-centric memory operations, and updates the coherence state appropriately at each cache level. The technical solution ensures that commands to implement the selective cache flushing are ordered before the memory-centric memory operation at the completion level of the memory-centric memory operation.