Selective Capping Layer Deposition on Semiconductor Interconnects
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Solution Overview
Problem
Current methods for selectively depositing metallic capping layers over metallic interconnects in semiconductor devices face challenges due to unwanted interactions between deposition precursors and barrier materials, leading to loss of selectivity and electrical shorts.
Innovation Solution
A method involving selective chemical vapor deposition using tungsten hexafluoride and hydrogen as precursors, with a pre-treatment process to remove passivation layers and contaminants, followed by exposure to a metal halide precursor and a reducing agent precursor in a cyclical process to achieve precise deposition of tungsten, titanium, or tantalum capping layers over metallic interconnects while minimizing deposition on dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective metal deposition on metallic surfaces is used to deposit capping layer over interconnect, then deposition selectivity is improved, but unwanted interactions with barrier material cause loss of selectivity and electrical shorts
Solution Approach 1:
A passivation layer is deposited over the barrier material before the selective metal deposition process. This preliminary action protects the barrier material from unwanted interactions with the metal precursor, preventing loss of deposition selectivity and avoiding electrical shorts while enabling reliable capping layer formation
Solution Approach 2:
The passivation layer acts as an intermediary between the barrier material and the metal precursor. It selectively blocks the precursor from reacting with the barrier material while allowing the deposition process to proceed selectively over the interconnect, thus maintaining both selectivity and reliability
2Manufacturing precision
If continuous metallic film deposition followed by lithography and etch patterning is used, then complete coverage is achieved, but process time and cost increase
Solution Approach 1:
The patent extracts and removes the time-consuming lithography and etch patterning steps from the process by using selective metal deposition. The metal precursor is made to deposit only where needed (over the interconnect) through selective reaction, eliminating subsequent patterning operations while maintaining complete coverage
Solution Approach 2:
The deposition process is made self-patterning through the selective reaction between the metal precursor and the interconnect surface. The system automatically deposits metal only in the desired locations without requiring external patterning intervention, reducing process complexity and time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains high selectivity during the deposition process, reducing unwanted metal deposition on dielectric materials and preventing electrical shorts, thereby ensuring reliable and efficient capping layer formation.
Implementation Method 1
selective chemical vapor deposition using tungsten hexafluoride and hydrogen as precursors, with a pre-treatment process to remove passivation layers and contaminants, followed by exposure to a metal halide precursor and a reducing agent precursor
Data Source
AI summary
A method of selectively depositing a capping layer structure on a semiconductor device structure is disclosure. The method may include; providing a partially fabricated semiconductor device structure comprising a surface including a metallic interconnect material, a metallic barrier material, and a dielectric material. The method may also include; selectively depositing a first metallic capping layer over the metallic barrier material and over the metallic interconnect material relative to the dielectric material; and selectively depositing a second metallic capping layer over the first metallic capping layer relative to the dielectric material. Semiconductor device structures including a capping layer structure are also disclosed.