Selective Catalyst Removal for Ni-Based Plating in Semiconductor Recesses

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Solution Overview

Problem

The existing methods for forming Cu wiring layers in semiconductor devices often result in voids and increased electric resistance due to the need for a barrier layer, which also increases manufacturing costs and processing complexity, especially as wiring miniaturization advances.

Innovation Solution

A method is developed to form a Ni-based metal plating layer within a recess on a substrate using an electroless plating process, where a catalyst layer is selectively formed and removed to prevent plating on the substrate surface, allowing for a more efficient and cost-effective process by eliminating the need for a barrier layer and reducing CMP processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a barrier layer is formed to suppress Cu diffusion, then reliability is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvediffusion suppressionVSAvoidnumber of layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the barrier layer from the wiring structure, replacing Cu with Ni-based metal that inherently suppresses diffusion into the insulating layer. This eliminates the need for a separate barrier layer while maintaining reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the material parameter from Cu to Ni-based metal, which has different diffusion characteristics. This material substitution allows the wiring to function without a separate barrier layer, reducing device complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a barrier layer is formed to suppress Cu diffusion, then reliability is improved, but electric resistance increases

Engineering Contradiction:
Improvediffusion suppressionVSAvoidelectric resistance
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

By removing the barrier layer entirely and using Ni-based metal that naturally suppresses diffusion, the patent eliminates the source of high electric resistance associated with barrier layers, achieving both reliability and low resistance.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If catalyst layer is formed on the entire substrate surface, then plating process is simplified, but manufacturing cost increases due to required CMP processing

Engineering Contradiction:
Improveplating process simplicityVSAvoidCMP processing time
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent applies local quality by forming the catalyst layer only within the recess regions where plating is needed, rather than on the entire substrate surface. This selective formation is achieved through the two-stage process of forming a full catalyst layer then removing it from non-recess areas, enabling plating to occur only where required without subsequent CMP processing.

Inventive Principle:
Principle #3Local quality

4Ease of manufacture

If Cu is used as wiring material, then established process is maintained, but void formation occurs and barrier layer is required

Engineering Contradiction:
Improveprocess compatibilityVSAvoidvoid formation
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent changes the material parameter from Cu to Ni-based metal, which exhibits different plating characteristics. This substitution eliminates void formation issues while maintaining electroless plating process compatibility, and additionally eliminates the need for a barrier layer.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of a Ni-based metal plating layer within the recess without forming it on the substrate surface, minimizing extra plating and reducing manufacturing costs and processing time, while achieving low electric resistance comparable to Cu wiring layers.

Implementation Method 1

a catalyst layer serving as a catalyst of a reductive precipitation reaction

Methodology Applied
Scientific EffectCatalysis: Catalysis

Implementation Method 2

catalyst of a reductive precipitation reaction

Methodology Applied
Scientific EffectReductive precipitation reaction: Precipitation

Data Source

PatentUS9711363B2Plating method, recording medium and plating system
Publication Date: 2017.07.18 TOKYO ELECTRON LTD
  • US9711363B2 patent drawing
  • US9711363B2 patent drawing
  • US9711363B2 patent drawing

AI summary

A plating method includes forming a catalyst layer 118 on a surface of a substrate including an inner surface of a recess 112; drying the substrate having the catalyst layer formed thereon such that an inside of the recess is dried as well; removing the catalyst layer at least on the surface of the substrate at the outside of the recess by supplying a processing liquid, which is configured to dissolve a material of the surface of the substrate, onto the surface of the substrate while rotating the dried substrate and while preventing or suppressing the processing liquid from being introduced into the dried inside of the recess; and forming a plating layer 119 on the inside of the recess, at which the catalyst layer is not removed, by an electroless plating process.