Selective Clock Delay Circuit for Hold Time Compliance
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Solution Overview
Problem
Synchronous circuits often face hold time violations due to timing requirements not being met, which can be challenging to address with existing methods that either require increasing path lengths or adding delay circuitry.
Innovation Solution
A variable clock delay logic circuit is introduced, which generates multiple delayed clock signals with varying delays and allows for programmable selection of these signals to logic circuits and input registers, enabling time borrowing and pipelining to satisfy timing requirements without introducing hold violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If path length is increased to fix hold time violations, then hold time requirements are met, but circuit delay increases and performance deteriorates
Solution Approach 1:
The patent applies local quality by providing different clock delay amounts to different registers based on their specific timing requirements. Each register receives a customized clock signal with an optimized delay amount, allowing hold time violations to be fixed locally without globally increasing circuit delay. This is achieved through a control circuit that selectively applies delay elements to specific clock paths based on detected timing violations.
Solution Approach 2:
The patent implements dynamics by making the clock delay amount adjustable and reconfigurable. The delay elements can be dynamically controlled to provide variable delay amounts, allowing the system to adapt to different timing requirements and operating conditions. This dynamic adjustment capability enables the circuit to optimize performance while maintaining hold time compliance.
2Reliability
If clock speed is reduced to fix setup time violations, then setup time requirements are met, but circuit performance and throughput decrease
Solution Approach 1:
The patent applies local quality by providing different clock delay amounts to different registers based on their specific timing requirements. Each register receives a customized clock signal with an optimized delay amount, allowing hold time violations to be fixed locally without globally increasing circuit delay. This is achieved through a control circuit that selectively applies delay elements to specific clock paths based on detected timing violations.
Solution Approach 2:
The patent implements dynamics by making the clock delay amount adjustable and reconfigurable. The delay elements can be dynamically controlled to provide variable delay amounts, allowing the system to adapt to different timing requirements and operating conditions. This dynamic adjustment capability enables the circuit to optimize performance while maintaining hold time compliance.
3Reliability
If delay circuitry is added to fix hold time violations, then hold time requirements are met, but circuit complexity increases
Solution Approach 1:
The patent applies universality by using a single control circuit to manage multiple clock paths and registers. The control circuit can selectively apply delay elements to any register that experiences hold time violations, providing a unified solution for the entire circuit rather than requiring separate delay circuitry for each register. This multi-functional approach reduces overall circuit complexity.
Solution Approach 2:
The patent implements the principle of discarding and recovering by conditionally enabling or disabling delay elements based on whether hold time violations are detected. When no violations occur, the delay elements are discarded (disabled) to minimize circuit complexity. When violations are detected, the delay elements are recovered (enabled) to fix the specific timing issues, then can be discarded again once fixed.
Data Source
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AI summary
The disclosed circuit arrangements include a logic circuit (105), input register logic (104) coupled to the logic circuit and including a first plurality of bistable circuits (202) and a control circuit (102) coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals (142, 148, 306, 308, 320, 326, 414, 416) from an input clock signal (150). The plurality of delayed clock signals include a first delayed clock signal (142, 148, 306, 308, 320, 326, 414, 416) and a second delayed clock signal (142, 148, 306, 308, 320, 326, 414, 416). The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic (302) circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.