Selective CMP for Polysilicon Thickness Control in IC Fabrication
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Solution Overview
Problem
The existing methods for fabricating integrated circuits require additional masking and etching steps to prevent polishing of polycrystalline silicon layers in logic areas during chemical mechanical polishing, increasing time and cost due to the need for protective material layers, which is undesirable.
Innovation Solution
The method employs a sequence of chemical mechanical polishing steps using both hard and soft pads, or differently selective chemical polishing slurries, to remove the capping layer from memory regions while maintaining it over logic regions, thereby eliminating the need for extra masking and etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a protective material layer is deposited over the device and removed only from memory devices prior to polishing, then the desired polycrystalline silicon thickness is maintained in logic areas, but the deposition of the extra protective material layer requires an extra masking and etching step which increases time and cost
Solution Approach 1:
The method performs preliminary actions by forming the memory device structure and polycrystalline silicon layer before logic device formation, then uses selective CMP to remove the polycrystalline silicon layer only from memory regions where it is needed, eliminating the requirement for protective masking layers and associated etching steps
Solution Approach 2:
The invention applies local quality by making the polycrystalline silicon layer selectively removable only from specific regions (memory devices) through controlled CMP processes, while leaving it intact in logic regions where it serves as a gate electrode, thereby achieving region-specific material removal without global protective masking
2Manufacturing precision
If a protective material layer is deposited over the device and removed only from memory devices prior to polishing, then the desired polycrystalline silicon thickness is maintained in logic areas, but the extra masking and etching steps increase fabrication cost
Solution Approach 1:
The method performs preliminary actions by forming the memory device structure and polycrystalline silicon layer before logic device formation, then uses selective CMP to remove the polycrystalline silicon layer only from memory regions where it is needed, eliminating the requirement for protective masking layers and associated etching steps
Solution Approach 2:
The invention extracts and eliminates the unnecessary protective material layer deposition and masking/etching steps from the fabrication process by using selective CMP to directly remove material only where needed, thereby simplifying the manufacturing process and reducing costs
3Productivity
If the physical size of integrated circuit devices is reduced to increase density, then greater capability in smaller consumer products is achieved, but the likelihood that processes employed in the fabrication of one device may adversely affect other devices increases due to increased proximity
Solution Approach 1:
The invention applies local quality by making the polycrystalline silicon layer selectively removable only from specific regions (memory devices) through controlled CMP processes, while leaving it intact in logic regions where it serves as a gate electrode, thereby achieving region-specific material removal without global protective masking
Solution Approach 2:
The method performs preliminary actions by forming the memory device structure and polycrystalline silicon layer before logic device formation, then uses selective CMP to remove the polycrystalline silicon layer only from memory regions where it is needed, eliminating the requirement for protective masking layers and associated etching steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of processing steps, saving time and cost while ensuring the desired polysilicon thickness is maintained in logic areas, thus improving the efficiency of integrated circuit fabrication.
Implementation Method 1
removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region
Data Source
AI summary
Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process.