Selective Coherence State Update in Cache Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multiprocessor systems, the existing cache coherence protocols face performance issues due to unnecessary communication between caches during store operations, leading to increased latency and power consumption when updating coherence states, particularly when a cache transitions from the M state to the T state and back.
Innovation Solution
The introduction of additional coherence states, such as Mu, allows caches to retain write authority and avoid unnecessary transitions, enabling caches to update coherence states selectively based on store instructions with specific policies, such as the CS field in store requests or MSR settings, to manage coherence states more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherence protocols update coherence states for every store operation, then cache coherency is maintained, but communication overhead and latency increase
Solution Approach 1:
The patent introduces a new coherence state parameter (Mu state) that modifies the traditional MESI protocol. When a cache line is in the Mu state, it indicates that the cache has write authority and other caches have invalid copies, allowing store operations to proceed without full coherence protocol transitions. This parameter change enables selective updating of coherence states based on the specific store operation characteristics.
Solution Approach 2:
The patent applies partial action by selectively updating coherence states only when necessary. Instead of updating coherence states for every store operation, the system determines whether a coherence state update is needed based on the current state and the store operation type. This partial updating approach reduces unnecessary communication overhead while maintaining required coherency.
2Reliability
If cache coherence protocols transition between M and T states for every store, then coherence is maintained, but power consumption increases
Solution Approach 1:
The introduction of the Mu coherence state creates a new parameter in the state machine that allows caches to remain in a modified state without transitioning to T state for certain store operations. This parameter change reduces the frequency of state transitions, thereby reducing power consumption associated with coherence protocol operations while maintaining coherency requirements.
Solution Approach 2:
The patent reduces power consumption by performing only the necessary coherence actions. When a store operation occurs on a cache line in Mu state, the system determines that full coherence protocol transitions are not needed, thus avoiding unnecessary power-consuming operations while still maintaining required coherency for the specific operation.
3Reliability
If caches communicate with each other for every store operation, then coherence is ensured, but system performance decreases
Solution Approach 1:
The Mu coherence state parameter enables caches to independently handle certain store operations without initiating inter-cache communications. When a cache line is in Mu state and a store operation occurs, the cache can update its local copy without notifying other caches, thus improving system performance by reducing communication overhead while maintaining coherency through the state parameter tracking.
Solution Approach 2:
The patent implements partial communication by selectively determining when inter-cache communication is necessary. Instead of communicating for every store operation, the system evaluates the current coherence state and the store operation characteristics to determine whether communication is required. This partial communication approach maintains coherency where needed while improving overall system performance by eliminating unnecessary communications.
Data Source
AI summary
A data processing system includes a processor core and a cache memory storing a cache line associated with a coherence state field set to a first of multiple modified coherence states. The processor core executes a store instruction including a field having a setting that indicates a coherence state update policy and, based on the store instruction, generates a corresponding store request including the setting, store data, and a target address. Responsive to the store request, the cache memory updates data of the cache line utilizing the store data. The cache memory refrains from updating the coherence state field based on the setting indicating a first coherence state update policy and updates the coherence state field from the first modified coherence state to a second modified coherence state based on the setting indicating a second coherence state update policy.