Selective Compilation of Simulation Models for Digital Circuit Monitoring

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Solution Overview

Problem

In digital design processes, verifying the logical correctness of complex digital circuits before fabrication is challenging due to the need for simulation, as actual building and correction of mistakes in integrated circuits are costly and time-consuming.

Innovation Solution

A method and system for building an instrumented simulation executable model using hardware description language (HDL) that allows for comprehensive monitoring of digital circuit designs by instantiating instrumentation entities within design entities, enabling accurate monitoring of design parameters without being compiled as part of the design, and allowing for platform and simulator independence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If comprehensive instrumentation is added to monitor all design parameters, then measurement precision improves, but device complexity increases

Engineering Contradiction:
Improvemonitoring accuracyVSAvoidmodel complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The simulation model is segmented into design entities and instrumentation entities. Each instrumentation entity independently monitors specific design parameters, allowing comprehensive monitoring without creating a monolithic complex system. The segmentation enables selective instrumentation where only necessary parameters are monitored at appropriate granularities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instrumentation entities act as intermediaries between the design entities and the monitoring system. These intermediary components capture and report design parameter values without directly modifying the core design logic, thereby maintaining measurement precision while isolating the complexity of instrumentation from the design entities themselves.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If instrumentation entities are compiled as part of the design, then integration improves, but ease of operation deteriorates

Engineering Contradiction:
ImproveintegrationVSAvoidplatform independence
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The instrumentation entity is designed with universal functionality that allows it to operate across different simulation platforms and HDL types without requiring platform-specific compilation. The instrumentation entity uses standardized interfaces and abstraction layers that enable portability while maintaining reliable integration with various design entities through consistent monitoring mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of information

If all design parameters are monitored, then information completeness improves, but loss of time increases

Engineering Contradiction:
Improveinformation completenessVSAvoidsimulation time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The monitoring approach applies local quality by selectively instrumenting only those design parameters and entities that are critical for verification. Rather than uniformly monitoring all parameters throughout the design, the instrumentation is concentrated on specific high-value targets, ensuring information completeness for critical parameters while reducing overall simulation overhead and time consumption.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8160857B2Selective compilation of a simulation model in view of unavailable higher level signals
Publication Date: 2012.04.17 SIEMENS INDUSTRY SOFTWARE INC
  • US8160857B2 patent drawing
  • US8160857B2 patent drawing
  • US8160857B2 patent drawing

AI summary

In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity.