Selective Conductive Barrier Layer Formation for Semiconductor Vias
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Solution Overview
Problem
Conductive barrier layers in semiconductor fabrication face challenges with resistance scaling, as minimum thickness specifications can render them non-conducting, leading to high via resistance and potential circuit failure.
Innovation Solution
A selective conductive barrier layer formation process using chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form aluminum oxide on sidewalls of vias, while avoiding formation on the bottom surface, combined with an in-situ thermal treatment at less than 400°C, to create a doped conductive layer that reduces via resistance and maintains an effective diffusion barrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conductive barrier layer is formed with minimum thickness specifications, then the diffusion barrier function is maintained, but the via resistance becomes high and the layer becomes non-conducting
Solution Approach 1:
The patent applies local quality by forming the aluminum oxide barrier layer selectively only on the sidewalls of the via, while intentionally avoiding formation on the bottom surface. This localized approach allows the sidewalls to have high barrier properties (preventing copper diffusion) while the bottom surface maintains conductivity for electrical connection, thus resolving the contradiction between barrier function and via conductivity
Solution Approach 2:
The via structure is segmented into different functional zones: the sidewalls are covered with the aluminum oxide barrier layer for diffusion prevention, while the bottom surface remains free of the barrier layer to maintain conductivity. This segmentation allows each region to fulfill its specific function without compromising the other, solving the contradiction between needing a barrier and needing conductivity
2Reliability
If a traditional TaN-based barrier layer is formed, then the diffusion barrier function is provided, but the via resistance increases due to non-conducting issues
Solution Approach 1:
The patent changes the material parameter from traditional TaN-based barrier layers to aluminum oxide formed through thermal treatment of an aluminum-containing layer. This material substitution, combined with selective formation on sidewalls only, fundamentally alters the electrical properties of the barrier layer, enabling it to provide both diffusion barrier function and acceptable via resistance by eliminating the non-conducting issues associated with TaN barriers
Solution Approach 2:
The patent uses an aluminum-containing layer as a precursor that is then thermally treated to form aluminum oxide in-situ. This approach copies the desired barrier layer structure selectively where needed (on sidewalls) while avoiding it where conductivity is required (bottom surface), achieving the dual functionality without the resistance problems of traditional TaN barriers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly lowers via resistance while maintaining an effective diffusion barrier, preventing copper diffusion and ensuring circuit integrity by forming a conductive barrier layer only on sidewalls, thus avoiding the non-conducting issues associated with traditional TaN-based barriers.
Implementation Method 1
applying a thermal treatment to the conductive oxygen scavenging layer to form a barrier layer on portions other than those contacting the first interconnect layer
Implementation Method 2
depositing a conductive oxygen scavenging layer... to form a barrier layer... preventing copper diffusion
Implementation Method 3
chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form aluminum oxide on sidewalls of vias
Implementation Method 4
depositing a conductive oxygen scavenging layer on sidewalls and adjacent surfaces of a trench and on sidewalls of a via
Data Source
AI summary
A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.