Selective Conformal Epitaxy for CMOS Fin Defect Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods face challenges in co-integrating lattice mismatched materials like III-V and IV materials on a Silicon substrate for CMOS implementation, leading to defects and performance issues in fin-based circuit devices due to large lattice mismatches and crystalline defects.
Innovation Solution
The approach involves growing buffer layers in a trench with a lattice constant equivalent to the channel layer, followed by the growth of device layers as cladding layers, and using selective and conformal epitaxy to integrate non-Si device heterolayers on patterned Si, ensuring the aspect ratio of the trench traps defects, allowing for p- and n-co-integration and reducing lattice mismatch defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lattice mismatched materials like III-V and IV materials are grown on Silicon substrate, then device performance and electron/hole movement are improved, but crystalline defects are generated due to large lattice mismatch
Solution Approach 1:
The patent divides the epitaxial growth process into two distinct segments: selective epitaxy for growing buffer layers in trenches, and conformal epitaxy for growing device layers on patterned substrates. This segmentation allows each process to be optimized independently, enabling high-quality material growth while managing lattice mismatch through controlled buffer layer formation
Solution Approach 2:
The patent applies different epitaxial growth conditions to different spatial locations: selective epitaxy is used in trench regions to grow buffer layers with specific orientations, while conformal epitaxy is used on exposed substrate areas for device layer growth. This local differentiation of growth quality enables simultaneous optimization for both defect reduction and device performance
2Ease of manufacture
If conventional epitaxial growth methods are used on patterned silicon, then manufacturing simplicity is maintained, but defects propagate throughout the trench and lead to yield issues
Solution Approach 1:
The patent performs preliminary action by growing buffer layers in trenches before forming the final device structures. This preliminary epitaxial growth establishes a defect-managed foundation that prevents subsequent defect propagation, ensuring high yield in the final device layers while maintaining a relatively simple overall process flow
3Object-generated harmful factors
If buffer layers are grown to reduce lattice mismatch, then defect generation is reduced, but additional process steps and complexity are introduced
Solution Approach 1:
The patent merges the buffer layer growth and device layer growth into a unified epitaxial process framework that uses the same fundamental equipment and chemistry. By combining selective and conformal epitaxy steps within a single process integration, the patent reduces overall process complexity while still achieving defect reduction through buffer layer formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces defects in fin-based devices, enabling the co-integration of n- and p-mos on a single silicon surface, improving device performance and yield by capturing defects in both directions within the trench, thus minimizing defects in active device layers.
Implementation Method 1
selective and conformal epitaxy to integrate non-Si device heterolayers on patterned Si
Data Source
AI summary
A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.