Selective Contact Capping for Oxidation-Sensitive CMOS SiGe Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced CMOS devices face challenges in manufacturability due to the sensitivity of high germanium concentration silicon germanium (SiGe) epitaxial layers to oxidation and wet etching chemistries, which can lead to removal of these layers in subsequent process steps, necessitating a method to protect them.
Innovation Solution
A method involving selective deposition processes to form a cap layer on the epitaxial layer without breaking the vacuum environment, ensuring protection from oxidation and contamination, and a multi-chamber processing system for integrated processing without exposing substrates to ambient environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high germanium concentration silicon germanium epitaxial layer is formed to minimize contact resistance, then contact resistivity is reduced into the 10^-9 Ω·cm2 regime, but the epitaxial layer becomes sensitive to oxidation and wet etching chemistries, leading to removal in subsequent process steps
Solution Approach 1:
A cap layer is deposited over the high germanium concentration silicon germanium epitaxial layer to serve as a protective intermediary. This cap layer prevents direct exposure of the sensitive epitaxial layer to oxidation and wet etching chemistries in subsequent processing steps, thereby maintaining the low contact resistivity while protecting against unwanted removal.
Solution Approach 2:
The deposition process is performed in a vacuum environment without breaking the vacuum, creating an inert atmosphere that prevents oxidation of the epitaxial layer during the formation of the cap layer. This maintains the compositional stability of the germanium-rich epitaxial layer while allowing protective cap layer formation.
2Reliability
If selective deposition processes are performed without breaking vacuum environment to protect the epitaxial layer, then oxidation and contamination are prevented, but process complexity and equipment requirements increase
Solution Approach 1:
Multiple deposition steps (forming the contact layer and forming the cap layer) are combined into a single continuous vacuum process without breaking the vacuum environment. This merging of steps maintains protection from oxidation and contamination while reducing the number of separate process interventions needed.
Solution Approach 2:
The vacuum deposition system is designed to perform multiple functions: depositing the high germanium concentration silicon germanium epitaxial layer, forming the contact layer, and forming the protective cap layer, all within the same vacuum environment. This multi-functionality reduces the need for separate processing equipment and steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively forms a cap layer that protects the epitaxial layer from oxidation and contamination, maintaining electrical integrity and reducing parasitic resistance, thereby enhancing the manufacturability and performance of advanced CMOS devices.
Implementation Method 1
performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening
Implementation Method 2
performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening
Implementation Method 3
an epitaxial layer of silicon germanium (SiGe) with a high germanium (Ge) concentration is sensitive to oxidation and also to wet etching chemistries, and thus may be removed in subsequent process steps
Data Source
AI summary
A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a hard mask on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening, and performing a second selective deposition process to form a cap layer on the contact layer.