Selective Contact Liner for DRAM Cell-to-Bit-Line Isolation

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Solution Overview

Problem

The reduction in size of memory cell structures in volatile memory devices, such as DRAM, leads to shorting issues between the cell contact and bit line contact, which compromises the integrity and functionality of the memory array.

Innovation Solution

Incorporating a protective liner within the memory cell structure that selectively avoids contact with the memory storage material while covering the bit line contact, thereby preventing shorting by forming a cavity and using a modified material to facilitate the deposition of the protective liner.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the size of memory cell structures is reduced, then the footprint and device size are decreased, but shorting occurs between cell contact and bit line contact

Engineering Contradiction:
Improvefootprint of memory deviceVSAvoidintegrity of memory array
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces a protective liner that segments the cavity into isolated regions, separating the bit line contact from the cell contact and memory storage material. This segmentation prevents direct contact between conductive elements while maintaining the reduced form factor of the memory device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protective liner acts as an intermediary barrier between the bit line contact and the cell contact/memory storage material. By placing this intermediate layer in the cavity, the patent prevents harmful direct contact while allowing the structure to maintain its compact size.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a protective liner is added to prevent shorting, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveaccess reliabilityVSAvoidstructure of memory cell
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protective liner is implemented as a thin film structure that conformally coats the cavity surfaces. This thin film approach provides the necessary protection against shorting while minimizing the added complexity and space requirements, as the liner forms as a thin conformal layer rather than a bulky structure.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables size reduction of memory arrays without unintentional shorting, enhancing access reliability and extending the life of electronic devices by preventing electrical connections between the cell and bit line contacts.

Implementation Method 1

forming a protective liner in the second cavity, wherein deposition of the protective liner is impeded over the portion of the sidewall of the second cavity

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20260025986A1Selective memory cell contact liner
Publication Date: 2026.01.22 MICRON TECHNOLOGY INC
  • US20260025986A1 patent drawing
  • US20260025986A1 patent drawing
  • US20260025986A1 patent drawing

AI summary

Methods, systems, and devices for a selective memory cell contact liner are described. A memory array may implement a protective liner within a memory cell structure including a cell contact for coupling memory storage material with an access device, a bit line associated with accessing the memory cell structure, and a bit line contact associated with activating the bit line. Forming the memory cell structure with the protective liner may include forming memory storage material, insulative material around the memory storage material, the bit line contact, the bit line, and the cavity. Then, a portion of the memory storage material may be replaced with a material associated with impeding deposition of the protective liner. The protective liner may be deposited within the cavity such that the bit line contact is covered by the protective liner but the memory storage material is not covered by the protective liner.