Selective CPU Reset in Multi-Component Systems via Local Judge Units
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Solution Overview
Problem
In multi-CPU systems connected via a common bus, simultaneous resetting of all CPUs leads to data loss and processing inefficiency, as existing methods either require manual operator intervention or automatic resetting without operator control, disrupting normal operations.
Innovation Solution
A multi-component system with a first reset signal generating unit, condition detection units (watchdog timers), and judge units that allow selective CPU resetting based on abnormal condition detection, enabling operator-controlled CPU reset and data security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all CPU modules are simultaneously reset in response to a reset signal, then the abnormal CPU can be reset, but normally executing CPU modules are also reset causing data loss and processing inefficiency
Solution Approach 1:
The patent divides the reset control into component-level segments. Each component has its own judge unit that independently determines whether to accept the reset signal based on local CPU condition detection. This segmentation prevents the reset signal from affecting all components uniformly, allowing selective resetting of only abnormal CPUs while preserving data in normally operating components.
Solution Approach 2:
The patent implements local quality by making each component's response to the reset signal dependent on its local CPU condition. The judge unit in each component evaluates whether its CPU is in an abnormal state and accordingly determines whether to accept the reset signal. This ensures that only components with abnormal CPUs undergo resetting, while components with normal CPUs continue processing without interruption and retain their processed data.
2Reliability
If manual detection of abnormal CPU condition is required, then selective reset is possible, but operator workload increases and response time delays occur
Solution Approach 1:
The patent implements self-service by enabling each component to autonomously monitor its own CPU condition through the watchdog timer and make independent decisions about reset acceptance. The judge unit automatically detects abnormal conditions and controls whether the component accepts reset signals without requiring manual intervention. This eliminates operator workload while maintaining selective reset capability.
Solution Approach 2:
The patent employs feedback mechanisms where the watchdog timer continuously monitors CPU operation and provides real-time status information to the judge unit. When abnormal conditions are detected, the feedback loop triggers appropriate responses either locally within the component or through the system controller, enabling automatic selective resetting without operator delay.
3Loss of time
If automatic CPU reset is implemented without operator control, then response time is reduced, but operator ability to confirm abnormality and secure data is lost
Solution Approach 1:
The patent applies dynamics by making the reset acceptance decision flexible and condition-dependent rather than fixed. The judge unit dynamically evaluates the CPU condition and determines whether to accept the reset signal based on real-time status. This dynamic approach allows automatic response to abnormal conditions while preserving operator control and decision-making capability when needed.
Solution Approach 2:
The patent implements preliminary action through the watchdog timer that continuously monitors CPU conditions and prepares to trigger appropriate responses before actual reset occurs. The system pre-evaluates abnormal conditions and can initiate secure data handling procedures before resetting, giving operators time to intervene if necessary while maintaining rapid response capability.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
To reset only the CPU (21, 31, 41) in a component (20, 30, 40) in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system (FIGs. 1 and 4), in which a plurality of components (20, 30, 40) each including at least a CPU (21, 31, 41) are connected via a common bus (50) to each other, includes a first reset signal generating unit (11) which generates a reset signal (Rs) by a switch operation to send the reset signal to respective components and a judge unit (23, 33, 43) which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.