Selectively Connected Data Lines in Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices face challenges in efficiently programming and sensing data across multiple-bit-per-cell modes due to limitations in selectively connecting data lines, which affects the speed and accuracy of data storage and retrieval.
Innovation Solution
The implementation of a transistor that selectively connects data lines, allowing for efficient programming and sensing operations across different modes by using page buffers to manage voltage levels and access lines, thereby facilitating multi-bit data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional data line connection methods are used in flash memory devices, then device complexity is reduced, but programming speed and reading speed are limited
Solution Approach 1:
The patent implements dynamic data line connections using transistors that can selectively connect or disconnect data lines based on operational mode. The first transistor connects the first data line to the second data line during programming operations, while the second transistor connects the first data line to the sense amplifier during reading operations. This dynamic reconfiguration enables the system to achieve higher programming and reading speeds by optimizing the data path for each specific operation type.
2Productivity
If selective data line connection is implemented for multi-bit operations, then programming and reading efficiency improve, but device complexity increases
Solution Approach 1:
The patent employs transistors that serve multiple functions: the first transistor acts as both a data line selector during programming and a signal router during reading operations. The second transistor similarly functions as a connection switch for the sense amplifier. This multi-functionality allows the same components to handle both programming and reading operations efficiently, improving productivity while controlling the increase in device complexity through component reuse.
Solution Approach 2:
The patent introduces intermediate connection structures including transistors and data line coupling mechanisms that mediate between the memory cells, data lines, and sense amplifiers. These intermediaries enable selective signal routing and isolation, allowing efficient multi-bit programming and reading operations by controlling which data lines are actively connected to which components at any given time.
Data Source
AI summary
Memory devices include a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line, thereby permitting connecting the first and second data lines in series before programming or sensing memory cells of the first and second strings of memory cells.