Selective Data Reduction for Circuit Verification Hotspot Analysis
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Solution Overview
Problem
As electronic designs increase in complexity, manual interpretation of performance data for functional verification becomes impractical due to the large amount of data and complex inter-relationships between design elements, making it difficult to identify and address performance hotspots effectively.
Innovation Solution
A computing system with a design verification tool that collects performance data during functional verification and uses a performance visualization tool to generate profile presentations, which can then apply selective data reduction to refine the presentation and highlight performance hotspots, allowing for the identification of contributing design elements and their interrelationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If performance profiling tools collect and organize data for whole designs and full duration of simulation run, then comprehensive performance data is obtained, but the amount of data becomes too large for manual interpretation and root cause analysis becomes impractical
Solution Approach 1:
The patent segments the comprehensive performance data into hierarchical groups organized by design elements (modules, components, functions). This segmentation transforms the overwhelming monolithic data set into manageable hierarchical segments that can be systematically analyzed, allowing manual interpretation while preserving comprehensive coverage of the entire design.
Solution Approach 2:
The patent introduces a hierarchical dimension to organize performance data, creating multiple levels of abstraction from individual design elements up to complete design modules. This dimensional organization allows analysts to navigate from detailed micro-level data to aggregated macro-level summaries, making comprehensive data interpretable without loss of information.
2Ease of operation
If attempts are made to filter the organized data into a manageable size, then data volume is reduced, but the multiple inter-relationships between design elements become obfuscated and root cause analysis is complicated
Solution Approach 1:
The patent implements a nested hierarchical structure where design elements are organized in nested groups from individual components to modules to complete design units. Each level contains and is contained by higher levels, preserving the inter-relationships between design elements while providing manageable views at each nesting level. The hierarchical relationships explicitly maintain the contextual connections between elements.
Solution Approach 2:
The hierarchical grouping structure acts as an intermediary between the complete detailed data and the analyst. Rather than directly filtering away data, the hierarchical structure mediates by organizing data into meaningful groups that preserve inter-relationships while presenting manageable information at each level of the hierarchy.
Data Source
AI summary
This application discloses a computing system implementing a design verification tool to perform functional verification on a circuit design describing an electronic device and collect samples of performance data during the functional verification. The computing system can also include a performance visualization tool to generate a profile presentation based on the samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot. The performance visualization tool can receive a data reduction request based on the performance hotspot annunciated by the profile presentation. The data reduction request can identify a subset of the performance data in the profile presentation. The performance visualization tool can generate a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.