Selective Data Verification in Multi-Bit Semiconductor Memory
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Solution Overview
Problem
Conventional data verification methods in multi-level flash memory devices become inefficient as the number of data bits increases, requiring sequential comparison of threshold voltages with all reference levels, which leads to slow verification times and potential operational failures.
Innovation Solution
A data verification method that selectively and adaptively verifies write data in a multi-bit memory cell by comparing write data reference bits with external data bits, only verifying target bits if the comparison is positive, thereby reducing the number of necessary comparisons and improving verification speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential comparison of threshold voltages with all reference levels is performed, then data verification completeness is ensured, but verification time increases significantly
Solution Approach 1:
The patent divides the data verification process into two stages: a preliminary comparison stage that checks reference bits against external data, and a conditional verification stage that only verifies target bits if the preliminary comparison passes. This segmentation allows the system to avoid unnecessary verification operations while maintaining completeness when needed.
Solution Approach 2:
The patent applies partial action by selectively verifying only the necessary bits (target bits) rather than all bits. The reference bits are compared first to determine whether full verification is needed, and only then are the target bits verified. This reduces the number of operations when data is correctly written while maintaining verification completeness when necessary.
2Measurement precision
If all data bits are verified sequentially, then verification accuracy is maintained, but operational efficiency decreases
Solution Approach 1:
The patent makes the verification process dynamic by adjusting the verification scope based on the comparison results of reference bits. If the reference bits match the external data, the system dynamically proceeds to verify target bits. If they don't match, the system dynamically stops verification. This dynamic adjustment optimizes both accuracy and efficiency.
Solution Approach 2:
The patent performs preliminary comparison of reference bits against external data before verifying target bits. This preliminary action serves as a filter that prevents unnecessary verification operations, thereby improving operational efficiency while maintaining verification accuracy through the subsequent target bit verification when needed.
3Reliability
If conventional verification methods are used in multi-level flash memory, then data integrity is ensured, but the complexity of verification operations increases
Solution Approach 1:
The patent segments the verification operations into reference bit comparison and target bit verification, reducing the complexity of the overall verification process. By dividing the verification task into manageable parts with clear conditional logic, the system maintains data integrity while simplifying the verification operation complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time required for data verification by selectively verifying only necessary bits, enhancing the operational efficiency of multi-bit data storage in semiconductor memory devices.
Implementation Method 1
The cell transistor is programmed or erased using an electrical charge transfer mechanism called Fowler-Nordheim (F-N) tunneling.
Implementation Method 2
electrons are accumulated on the floating gate FG of the memory cell during a program operation, and are removed from the floating gate FG during an erase operation
Implementation Method 3
a strong electric field is formed between the floating gate and bulk due to a large voltage difference between these two elements
Implementation Method 4
electrons stored on the floating gate migrate to the bulk due to the F-N tunneling effect
Implementation Method 5
the threshold voltage of the programmed cell transistor is changed in a positive direction. the threshold voltage of the erased cell transistor is changed in a negative direction
Data Source
AI summary
A semiconductor memory device storing multi-bit write data and a related method of verifying data programmed to a memory cell are disclosed. The method compares a write data reference bit selected from the write data with a corresponding external data bit indicative of an intended write data bit value, and verifies a target bit selected from the write data only upon a positive comparison between the write data reference bit and the corresponding external data bit.