Selective Deposition of Charge Storage Regions in 3D NAND
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Solution Overview
Problem
Current three-dimensional vertical NAND strings face challenges in achieving high density and efficient fabrication due to complex and time-consuming processes, particularly in forming active regions and charge storage regions, which limits their bit capacity and manufacturing efficiency.
Innovation Solution
A method involving the formation of alternating layers of different materials over a substrate, where the semiconductor material is selectively deposited and etched to create vertically spaced charge storage regions with varying thicknesses based on incubation times on different materials, allowing for efficient formation of semiconductor channels and charge storage regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to form active regions with sidewall spacers and etching, then charge storage regions can be formed, but the process becomes relatively difficult and time consuming
Solution Approach 1:
The patent extracts and removes the complex sidewall spacer formation and etching steps from the conventional process. Instead, it directly forms charge storage regions by selectively depositing semiconductor material in the front side recesses, eliminating the time-consuming intermediate steps while achieving the same functional result.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the front side recesses and selectively depositing semiconductor material before the final channel formation. This preliminary placement of charge storage regions simplifies subsequent processing steps and reduces overall fabrication time.
2Quantity of substance
If conventional NAND string structures are used, then one bit per cell is achieved, but high density and bit capacity are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar structures to three-dimensional vertical structures with front side recesses. This dimensional change allows multiple charge storage regions to be stacked vertically within the same footprint, dramatically increasing bit capacity per cell while maintaining manufacturing efficiency through selective material deposition.
Solution Approach 2:
The patent implements nesting by placing multiple charge storage regions within the front side recesses at different vertical levels. These nested regions are embedded within the three-dimensional structure, allowing high-density storage without proportionally increasing the device footprint or complicating the manufacturing process.
3Manufacturing precision
If uniform semiconductor material thickness is deposited, then simple deposition is achieved, but selective charge storage region formation is impossible
Solution Approach 1:
The patent applies local quality by creating front side recesses with specific geometries that cause semiconductor material to deposit with varying thicknesses in different locations. The recesses are designed so that material accumulates preferentially in certain areas, enabling selective charge storage region formation through a single deposition process without requiring complex localized control.
Solution Approach 2:
The patent changes the geometric parameters of the front side recesses to control material deposition patterns. By adjusting recess depth, width, and shape, the process exploits natural deposition physics to achieve selective thickness variations, converting a simple deposition process into a precision tool for pattern formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density monolithic three-dimensional NAND strings with improved manufacturing efficiency and bit capacity, reducing the complexity of the fabrication process while enhancing the structural integrity of the semiconductor device.
Implementation Method 1
a thickness of the first layer of semiconductor material formed over the second material layers is greater than a thickness of the first layer of semiconductor material formed over the first material layers due to a difference in an incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material
Data Source
AI summary
Methods of fabricating semiconductor devices, such as monolithic three-dimensional NAND memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide.