Selective Dielectric Deposition for Precise Gate Cut Formation
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Solution Overview
Problem
As fin pitch scales down, precision gate cuts in fin-type field-effect transistors become challenging, leading to incomplete formation and unwanted over-etch issues, where gate contacts may land on dielectric material, affecting device performance.
Innovation Solution
A method involving forming a gate structure with a dielectric cap, patterning an opening through it, depositing spacers to shorten the opening, and etching to create a cut that divides the gate electrode into sections, followed by depositing a dielectric pillar to isolate the sections, allowing for precise disconnection without over-etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process is extended to provide an over-etch to ensure complete gate cut formation, then the gate sections are fully disconnected, but the dimensions of the gate cuts increase such that gate contacts may land on the dielectric material filling the gate cuts
Solution Approach 1:
A dielectric cap is formed over the gate structure before the gate cut etching process. This preliminary action creates a protective layer that prevents the etching process from extending beyond the desired cut location, thereby eliminating the need for over-etching while ensuring complete disconnection of gate sections.
Solution Approach 2:
The dielectric cap serves as an intermediary protective layer between the etching process and the gate structure. It acts as a mask that defines the precise boundaries of the gate cut, preventing lateral etching expansion while allowing vertical etching to complete the cut through the gate electrode.
2Productivity
If the fin pitch is scaled downward to increase device density, then more devices can be packed in an integrated circuit, but precision gate cuts become increasingly difficult to form completely
Solution Approach 1:
The dielectric cap is formed in advance before the gate cut process, providing a pre-defined protective boundary that becomes increasingly important as feature sizes scale down. This preliminary structure ensures that even at reduced pitch dimensions, the gate cuts can be formed completely and precisely without requiring excessive etching margins.
Solution Approach 2:
The invention changes the process parameters by introducing a dielectric cap layer with specific thickness and material properties that are optimized for scaled dimensions. This allows the gate cut process to maintain precision at smaller pitch values by controlling the etching depth and lateral spread through the cap's physical and chemical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and complete formation of gate cuts at small dimensions, ensuring full disconnection of gate sections without increasing cut dimensions, thus improving the accuracy and reliability of fin-type field-effect transistor fabrication.
Implementation Method 1
forming a dielectric cap over the gate structure
Implementation Method 2
selectively depositing a first dielectric spacer on the first surface of the first section of the dielectric cap and a second dielectric spacer on the second surface of the second section of the dielectric cap
Implementation Method 3
A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut
Implementation Method 4
depositing a dielectric pillar
Data Source
AI summary
Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.