Package Substrate With Selective Dielectric Layer Thickness

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In packaged electronic devices, the challenge lies in achieving void-free underfilling, particularly in small underfill gaps (<20 μm), which can lead to reliability failures and damage to the IC die during mounting due to the conflict between the need for a dielectric layer for adhesion and the risk of underfill voids and joint misalignment.

Innovation Solution

A package substrate with a thin dielectric layer in the die attach region and a thicker dielectric layer in non-die attach regions, allowing for increased underfill gap height while maintaining reliable adhesion and preventing shorting of adjacent conducting traces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dielectric layer (solder mask) is provided on the package substrate surface for underfill adhesion, then adhesion reliability is improved, but the gap height between IC die and substrate surface is reduced, causing underfilling voids and potential IC die damage

Engineering Contradiction:

Improveadhesion reliabilityVSAvoidgap height

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent applies different dielectric layer thicknesses in different regions: a first thickness in the die attach region and a second (thicker) thickness in non-die attach regions. This local differentiation allows the gap height to be sufficient in critical areas while maintaining adhesion where needed, resolving the contradiction between adhesion reliability and gap height.

Inventive Principle:

Principle #3Local quality

2Length of moving object

If the dielectric layer thickness is reduced to 10-15 μm to increase gap height, then underfilling quality is improved, but the dielectric layer cannot reliably hold conducting balls and voiding increases causing short circuits

Engineering Contradiction:

Improvegap heightVSAvoidconducting ball holding capability

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

The patent implements a thicker dielectric layer (second thickness) in non-die attach regions, which provides sufficient mechanical support for holding conducting balls and prevents voiding-induced short circuits, while the thinner first thickness in die attach regions maintains adequate gap height for underfilling.

Inventive Principle:

Principle #3Local quality

3Reliability

If a nominal dielectric layer thickness of 20 μm is used, then conducting ball holding capability is maintained, but the underfill gap height is reduced causing underfilling voids and IC die damage

Engineering Contradiction:

Improveconducting ball holding capabilityVSAvoidgap height

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent divides the dielectric layer into two thickness zones: a thinner first thickness in the die attach region to increase gap height for void-free underfilling, and a thicker second thickness in non-die attach regions to maintain conducting ball holding capability, thus resolving the contradiction.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8298874B2Packaged electronic devices having die attach regions with selective thin dielectric layer

Publication Date: 2012.10.30 TEXAS INSTRUMENTS INC

AI summary

A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.