Selective Dipole Oxide in GAA Transistors for Threshold Voltage Control
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Solution Overview
Problem
In gate all around transistors, it is challenging to achieve transistors with different selected threshold voltages without introducing unwanted variations in threshold voltages.
Innovation Solution
Incorporating dipole layers at the interfacial dielectric layer on semiconductor nanosheets, formed in a way that reduces unwanted variations in threshold voltages, allowing for transistors with distinct threshold voltages by using a dipole-inducing layer on the interfacial dielectric layer, which generates a dipole layer that modulates the effective work function and adjusts the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dipole layers are incorporated to achieve different threshold voltages in transistors, then threshold voltage tunability is improved, but unwanted dipole layer formation in unintended transistors causes threshold voltage variations
Solution Approach 1:
The patent applies local quality by making the dipole layer formation selective to specific transistor regions. Different transistor types (first type vs. second type) have different dipole layer configurations - some have dipole layers while others don't, allowing each region to have the specific threshold voltage characteristics it needs. This is achieved through selective deposition or formation processes that target specific transistor areas.
Solution Approach 2:
The patent segments the transistor population into different groups based on their dipole layer status. First transistors are configured with dipole layers while second transistors are configured without dipole layers, creating distinct segments with different threshold voltage characteristics. This segmentation allows independent optimization of threshold voltages for different transistor types within the same integrated circuit.
2Reliability
If dipole-inducing layer is added to adjust threshold voltage, then device performance is improved, but process complexity increases
Solution Approach 1:
The patent merges the dipole-inducing layer formation with existing gate dielectric layer deposition processes. The dipole-inducing layer is deposited as part of the gate dielectric stack formation sequence, combining multiple functions into a unified process flow. This integration reduces the need for separate, additional process steps while still achieving the desired dipole layer formation.
Solution Approach 2:
The dipole-inducing layer acts as an intermediary between the gate electrode and the channel region. This intermediate layer provides the threshold voltage tuning function without requiring direct modification of the channel or gate electrode, enabling indirect control of transistor characteristics through a mediating material layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases device performance and yield by reliably achieving different threshold voltages in transistors, ensuring no unwanted dipole layer formation in unintended transistors, thus maintaining threshold voltage consistency.
Implementation Method 1
Incorporating dipole layers at the interfacial dielectric layer on semiconductor nanosheets, formed in a way that reduces unwanted variations in threshold voltages, allowing for transistors with distinct threshold voltages by using a dipole-inducing layer on the interfacial dielectric layer, which generates a dipole layer that modulates the effective work function and adjusts the threshold voltage.
Data Source
AI summary
A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.