Selective Directory Update for Cache Coherency in Multiprocessors
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Solution Overview
Problem
In multiprocessor systems with directory-based caches, existing coherence schemes lead to excessive directory updates and invalidation requests, causing unnecessary bus traffic and performance degradation, especially in regions of memory that are read-only or not frequently written.
Innovation Solution
Implementing a read/write bit for each cache line to control when processors update the memory directory, limiting updates to only when the block has been accessed by multiple processors and written to, thereby reducing unnecessary directory updates and invalidation requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If directory-based coherence schemes are used to maintain cache coherency between processors, then cache coherency is maintained, but excessive directory updates and invalidation requests occur causing unnecessary bus traffic and performance degradation
Solution Approach 1:
The patent applies local quality by differentiating the treatment of cache blocks based on their specific characteristics - modified versus unmodified blocks. The read/write bit in the directory selectively marks blocks that have been written to, enabling the system to apply different update policies: full updates for modified blocks and selective updates for unmodified blocks. This localized differentiation reduces unnecessary directory updates while maintaining coherency where needed.
Solution Approach 2:
The patent changes the state parameter of cache blocks by introducing a read/write bit that tracks whether a block has been modified. This parameter change enables the coherence protocol to distinguish between blocks requiring coherency enforcement (modified) and those that don't (unmodified), thereby reducing invalidation traffic for read-only or shared blocks while maintaining reliability for writable blocks.
2Measurement precision
If presence bits are updated on every block replacement, then directory accuracy is maintained, but unnecessary bus traffic and directory updates occur
Solution Approach 1:
The patent applies local quality by updating presence bits selectively based on the specific characteristics of the replaced block. Instead of uniformly updating presence bits for all replacements, the system checks the read/write bit and only updates when necessary (for modified blocks). This localized approach maintains directory accuracy for blocks requiring coherency while avoiding unnecessary updates for blocks that don't require it.
Solution Approach 2:
The patent applies partial action by performing presence bit updates only when necessary rather than on every block replacement. The read/write bit serves as a filter that enables partial updates - updating presence bits for modified blocks that require coherency enforcement while omitting updates for unmodified blocks where such updates would be excessive and unnecessary.
Data Source
AI summary
Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.