Selective DRAM Chip Hibernation for Power Reduction
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Solution Overview
Problem
Dynamic random access memory (DRAM) in user devices consumes excessive battery power due to continuous refreshing, even when only one process is active while others are inactive, leading to high power consumption.
Innovation Solution
Implementing a system that selectively hibernates DRAM chips by allocating data from inactive processing operations to storage devices, allowing only active processing operations to maintain full power, thereby reducing battery power consumption and extending battery life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM chips continue to refresh data for all processes even when inactive, then data integrity is maintained, but power consumption increases excessively
Solution Approach 1:
The patent segments the DRAM system into multiple independently controllable DRAM chips, each dedicated to specific processes. This allows selective hibernation of individual chips based on process activity status, enabling data integrity maintenance for active processes while powering down chips for inactive processes to reduce overall power consumption.
Solution Approach 2:
The patent applies different power states to different DRAM chips based on local conditions (process activity). Active DRAM chips maintain full refresh operations for data integrity, while inactive DRAM chips enter hibernation mode with reduced or no refreshing, optimizing the balance between data integrity and power consumption locally for each chip.
2Speed
If data from inactive processes is kept in DRAM, then quick resumption is possible, but power is wasted on refreshing unused data
Solution Approach 1:
The patent dynamically adjusts the refresh rate and power state of each DRAM chip based on process activity status. When a process becomes inactive, its dedicated DRAM chip transitions from full refresh mode to hibernation mode, reducing energy consumption. When the process is activated again, the chip quickly resumes full refresh operations, adapting the refresh behavior to current system needs.
3Use of energy by moving object
If the entire DRAM is hibernated to save power, then power consumption decreases, but access to any data becomes slower
Solution Approach 1:
The patent divides the DRAM system into multiple independently manageable chips, each serving specific processes. This segmentation enables selective hibernation where only the chips corresponding to inactive processes are powered down, while chips for active processes remain fully operational. This resolves the contradiction by maintaining fast access speed for active data while reducing power consumption for inactive data.
Data Source
AI summary
Power consumption can be reduced by selective memory chip hibernation. For example, a computing device can allocate first data associated with a first processing operation of a user device to a first chip of a dynamic random access memory (DRAM) of the user device. The computing device can allocate second data associated with a second processing operation of the user device to a second chip of the DRAM of the user device. The computing device can determine the first processing operation has been inactive for a predetermined period of time and migrate the first data from the first chip of the DRAM to a storage device of the user device. The computing device can hibernate the first chip of the DRAM while maintaining power to the second chip of the DRAM for continuing to perform the second processing operation.