Duty Cycle Control Circuit With Selective Cells for Fast Clock Locking
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Solution Overview
Problem
Traditional duty cycle controlling circuits face issues such as high power consumption, large circuit size, slow locking time, duty cycle distortion, and limited accuracy due to power supply sensitivity and trade-offs in duty cycle correction and clock range.
Innovation Solution
A duty cycle controlling circuit comprising a duty cycle adjusting cell and a detecting module, utilizing a combination of inverters, transistors, and CMOS to generate precise clock signals with reduced forward path delay and improved accuracy, allowing for wide range duty cycle correction and ultra-low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional duty cycle controlling circuits are used, then duty cycle control function is provided, but power consumption is high
Solution Approach 1:
The duty cycle controlling circuit is divided into multiple independent duty cycle adjusting cells (first, second, third, fourth cells) that can be selectively activated. Only the necessary number of cells are enabled based on the required duty cycle range, reducing overall power consumption while maintaining control accuracy through the hierarchical structure of cells operating at different duty cycle ranges.
Solution Approach 2:
The circuit dynamically selects and activates specific duty cycle adjusting cells based on the required duty cycle correction range. The control logic enables or disables individual cells (e.g., enabling only the first cell for small corrections, or enabling first and third cells for larger corrections), optimizing power consumption according to actual operational needs while maintaining precision.
2Area of stationary object
If traditional duty cycle controlling circuits are used, then duty cycle control function is provided, but circuit region is large
Solution Approach 1:
The duty cycle controlling circuit is segmented into multiple specialized adjusting cells, each optimized for specific duty cycle ranges. This modular approach reduces the overall circuit region by activating only the necessary cells for each operation, rather than requiring all components to be simultaneously active or present in a single large circuit block.
Solution Approach 2:
The duty cycle adjusting cells are arranged in a nested hierarchical structure where cells operate at different duty cycle ranges (e.g., first cell for 0-20% correction, third cell for 20-40% correction). This nesting allows the circuit to achieve wide-range duty cycle control accuracy while minimizing circuit region by selectively engaging appropriate nested levels based on the required correction magnitude.
3Loss of time
If traditional duty cycle controlling circuits are used, then duty cycle control function is provided, but locking time is slow
Solution Approach 1:
The circuit dynamically adjusts its response characteristics by selectively activating different duty cycle adjusting cells based on the magnitude of duty cycle correction required. This dynamic configuration enables faster locking time for small corrections (using only the first cell with optimized parameters) while maintaining accuracy for larger corrections by engaging additional cells in the hierarchical structure.
4Measurement precision
If duty cycle correction accuracy is improved, then precision is higher, but clock range is reduced
Solution Approach 1:
The duty cycle adjusting cells are segmented to operate at different duty cycle ranges (e.g., first cell for 0-20% correction, second cell for 0-10% correction, third cell for 20-40% correction). This segmentation allows the circuit to achieve high precision within each segment's specific range while collectively covering a wide overall clock range through the combination of multiple specialized cells.
Solution Approach 2:
The control logic dynamically selects which duty cycle adjusting cells to activate based on the required duty cycle correction magnitude. For small corrections, only high-precision cells are enabled; for larger corrections, additional cells are engaged. This dynamic selection maintains high accuracy for the active cells while extending the overall adaptable clock range through the hierarchical structure.
Data Source
AI summary
A duty cycle controlling circuit for adjusting duty cycle of a target clock signal to a desired value, comprises: a first duty cycle adjusting cell, for receiving a first duty cycle control signal to adjust duty cycle of an input clock signal to generate a first output clock signal as the target clock signal; and a duty cycle detecting module, for generating the first duty cycle control signal according to the first output clock signal.


