Selective Dynamic ECC in Integrated Circuit Memory
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Solution Overview
Problem
Existing memory systems face challenges in maintaining reliability due to varying bit error rates across different memory cell groups, leading to inefficient use of redundant information and increased complexity or reduced reliability when storing multiple bits per cell.
Innovation Solution
A memory system that dynamically adjusts the amount of redundant information based on bit error rates, using error correction codes like LDPC, and employs a Gray code mapping to program threshold voltages, ensuring high reliability in data retrieval by generating extra data groups through XOR/XNOR operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are applied to all memory cell groups, then data reliability is improved, but hardware complexity and resource usage increase
Solution Approach 1:
The patent applies error correction codes selectively only to memory cell groups that exhibit high bit error rates, rather than uniformly to all memory cells. This localized approach maintains high data reliability for problematic regions while avoiding the hardware overhead of implementing ECC across the entire memory array, thus resolving the contradiction between reliability improvement and hardware complexity reduction.
Solution Approach 2:
The patent dynamically adjusts the application of error correction based on measured bit error rate parameters. By monitoring error rates and adapting the ECC deployment strategy accordingly, the system optimizes the balance between reliability and hardware resource usage, applying correction only when and where needed rather than using a fixed configuration for all memory regions.
2Reliability
If redundant information is increased for high error rate regions, then data reliability is improved, but storage capacity is reduced
Solution Approach 1:
The patent applies redundant error correction information only to specific memory cell groups that exhibit high bit error rates, rather than uniformly across all memory cells. This localized redundancy strategy improves reliability for problematic regions while minimizing the overall storage capacity penalty, as the majority of memory cells with low error rates do not require additional redundant bits.
Solution Approach 2:
The patent implements error correction with partial action by selectively applying it only to the extent necessary for high error rate regions. Rather than providing excessive redundancy across the entire memory array, the system applies just enough correction capability to handle the actual error conditions present in specific memory regions, optimizing the trade-off between reliability and storage capacity.
3Quantity of substance
If multiple bits per cell are stored, then storage density is improved, but bit error rates increase
Solution Approach 1:
The patent applies error correction codes selectively to memory cell groups that store multiple bits per cell and exhibit high bit error rates. By targeting ECC application to these specific high-density regions rather than uniformly across all memory cells, the system mitigates the reliability degradation caused by multi-bit storage while preserving the storage density benefits in affected regions.
Solution Approach 2:
The patent uses error correction codes to create redundant copies of data in high error rate regions. By generating and storing corrected versions of data from multi-bit cells, the system recovers from bit errors that occur in high-density storage regions, effectively copying protective information to counteract the increased error susceptibility of multi-bit per cell storage.
Data Source
AI summary
A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.