Selective ECC Updates for Low-Latency Cache Tag Writes
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Solution Overview
Problem
Conventional processor systems incur significant latency and processing overhead due to the need to re-compute all error correction code (ECC) bits during read-modify-write operations, especially in cache tag arrays where state bits change frequently, leading to unnecessary computation of ECC bits for address bits that remain unchanged.
Innovation Solution
Implementing dedicated ECC logic that only updates ECC bits in response to changes in state bits, while ignoring changes in address bits, thereby reducing the number of ECC bits to be recalculated and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all ECC bits are re-computed during read-modify-write operations, then error correction accuracy is maintained, but latency and processing overhead increase significantly
Solution Approach 1:
The patent segments the ECC computation process by dividing ECC bits into groups that are selectively updated based on which data bits have changed. Instead of recomputing all ECC bits, only the subset corresponding to changed data bits is updated, reducing computation time while maintaining error correction accuracy.
Solution Approach 2:
The patent applies partial action by computing only the necessary portion of ECC bits rather than all ECC bits. When only certain data bits change, the system computes only the corresponding ECC bits needed to maintain correction capability, avoiding unnecessary computation of other ECC bits.
2Reliability
If all ECC bits are re-computed for every state bit change in tag array, then error detection capability is maintained, but processing overhead increases
Solution Approach 1:
The patent segments the tag array into address bits and state bits, and further segments ECC computation based on which subset of bits has changed. This allows the system to maintain error detection capability while avoiding redundant computation of ECC bits associated with unchanged portions of the tag array.
Solution Approach 2:
The patent applies local quality by treating different portions of the tag array differently based on their change characteristics. State bits that change frequently trigger selective ECC updates, while address bits that change less frequently are handled differently, optimizing processing overhead based on local change patterns.
3Reliability
If complete ECC re-computation is performed, then error correction reliability is ensured, but computation time increases
Solution Approach 1:
The patent implements partial action by computing only the minimum necessary ECC bits required to maintain correction reliability. By analyzing which data bits have changed and computing only the corresponding ECC bits, the system achieves the same reliability outcome with reduced computation time.
Solution Approach 2:
The patent performs preliminary analysis to determine which ECC bits need updating before actual computation begins. By pre-identifying the subset of ECC bits that require computation based on changed data bits, the system avoids unnecessary computation and speeds up the overall process while maintaining reliability.
Data Source
AI summary
The present invention provides a method and apparatus for selectively updating error correction code bits. One embodiment of the method includes determining a first subset of a plurality of error correction code bits formed from a plurality of data bits in response to changes in a first subset of the data bits. The first subset of the plurality of error correction code bits is less than all of the plurality of error correction code bits.