Selective ECC Checkbit Generation for Memory Error Control
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Solution Overview
Problem
Data processing systems face challenges in detecting and correcting errors during data transfer and storage, particularly due to faulty memory modules, where existing error correction techniques either fail to detect errors at the memory device or complicate testing by correcting errors before they can be tested at the requesting module.
Innovation Solution
Implementing an end-to-end error detection and correction scheme with a memory device that generates ECC checkbits based on both data and memory addresses, allowing selective enabling and disabling of error detection and correction for write accesses, and using an ECC control register to manage access policies, enabling flexibility in error checking and testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed at the memory device for all write accesses, then data storage reliability is improved, but performance and testing capability deteriorate due to inability to inject errors for testing
Solution Approach 1:
The patent implements dynamic control of error correction functionality through an ECC control register that can be programmed to enable or disable error correction for different write access sizes. This allows the system to switch between error correction modes (full correction, selective correction, or no correction) depending on whether testing or normal operation is required, resolving the contradiction between reliability and testing capability
2Reliability
If error detection and correction is enabled for all data transfers, then system reliability is improved, but performance overhead increases due to additional processing
Solution Approach 1:
The patent applies error correction selectively based on write access size characteristics. By configuring the ECC control register, error correction can be enabled for specific data widths (e.g., only for writes smaller than a threshold size) while disabled for others. This local application of error correction reduces overall processing overhead while maintaining reliability for critical data transfers
Solution Approach 2:
The system changes the operational parameters of error correction by allowing dynamic configuration of the ECC control register with different access policies. This enables the system to adjust error correction behavior (enabled/disabled, selective/enabled) based on performance requirements, effectively trading off between reliability and productivity as needed
3Reliability
If end-to-end error detection is implemented, then errors during data transfer are detected, but complexity of the error correction system increases
Solution Approach 1:
The patent implements a universal error correction architecture where the same ECC module and control register handle both traditional memory error correction and end-to-end error detection for data transfers. This multi-functional design allows the system to perform error correction for memory operations and error detection for transfer operations using the same hardware resources, reducing overall system complexity while maintaining comprehensive error protection
Data Source
AI summary
Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.