Selective ECC Application for Memory in Neural Network Semiconductors
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Solution Overview
Problem
Existing error correction code (ECC) applications in artificial neural network-based system semiconductors increase memory region due to additional ECC memory regions and check bits, which can lead to inefficiencies and increased memory usage.
Innovation Solution
The method involves dividing memory cells into groups based on word lines and selectively applying ECC to specific memory cell arrays corresponding to each frame, while performing general write or read operations without ECC on remaining groups, adjusting the number of ECC applications based on fault handling time interval (FTTI) and frame processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC is applied to all memory cells, then reliability is improved, but memory region increases
Solution Approach 1:
The patent divides memory cells into multiple banks, with each bank containing multiple memory cell arrays. ECC is applied selectively to specific banks rather than all memory cells, segmenting the error protection coverage to reduce overall memory region while maintaining reliability for critical operations.
Solution Approach 2:
The patent applies different error correction strategies to different memory banks based on their specific requirements. Some banks use full ECC while others use reduced ECC or parity bits, creating local quality variations that optimize the balance between reliability and memory region usage.
2Reliability
If SEC-DEC ECC method is used, then reliability is improved, but memory region increases due to check bits
Solution Approach 1:
The patent implements partial ECC action by applying SEC-DEC only to specific memory banks that require high reliability, while using reduced ECC or parity bits for other banks. This partial application reduces the overall check bit overhead while maintaining adequate error protection where needed.
Solution Approach 2:
The patent changes the ECC parameters dynamically based on memory bank characteristics and operational requirements. Different memory banks use different ECC codes with varying check bit lengths, allowing optimization of the reliability-to-memory-region ratio by adjusting ECC parameters rather than using a uniform approach.
3Reliability
If multiple ECC circuits are added to alleviate adjacent memory cell failures, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments memory cells into multiple banks that can be independently managed by separate ECC circuits. This segmentation allows adjacent memory cell failures to be isolated to specific banks, preventing cascade failures while using a manageable number of ECC circuits rather than requiring one for every possible failure scenario.
Solution Approach 2:
The patent introduces bank-level control logic as an intermediary between the memory cell arrays and ECC circuits. This intermediary manages the interaction between multiple ECC circuits and memory banks, coordinating error correction operations and reducing the overall system complexity by providing a centralized control layer.
Data Source
AI summary
A method for applying error correction code (ECC) to a memory performed by an apparatus for applying ECC to a memory in an artificial neural network-based system semiconductor, includes dividing memory cells into a plurality of groups of memory cell arrays corresponding to first to n-th frames based on word lines, wherein n is a natural number greater than or equal to 2, performing an ECC write or read operation by applying ECC to a memory cell array of a group corresponding to each of the first to n-th frames, and performing a general write or read operation without applying ECC to the memory cell array of the remaining groups excluding the group corresponding to each of the first to n-th frames.