Selective Edge Phase Mixing for High-Frequency Clock Synchronization
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Solution Overview
Problem
Synchronous integrated memory devices face challenges in maintaining synchronization between internal and external clock signals as frequency increases, leading to phase shifts and duty cycle variations, which can cause operational failures.
Innovation Solution
The selective edge phase mixing apparatus and method, which includes a buffer and a selective edge phase mixing unit that adjusts the duty cycle of the clock signal using add and subtract duty signals, dynamically compensating for phase differences and duty cycle distortions to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the external clock signal is increased to improve processing speed, then the processing speed is improved, but phase shifts and duty cycle variations between internal and external clock signals increase causing synchronization failures
Solution Approach 1:
The patent changes the parameters of the internal clock signal by selectively adjusting the phase of specific edges (rising or falling edges) to match the external clock signal's phase characteristics. This involves modifying the duty cycle and phase alignment dynamically to compensate for frequency-related phase shifts and duty cycle variations, thereby maintaining synchronization reliability at higher processing speeds.
Solution Approach 2:
The patent implements dynamic edge selection and phase adjustment mechanisms that adapt the internal clock signal generation based on detected phase differences and duty cycle variations. The system dynamically chooses which edges to phase-mix and adjusts the mixing ratio to optimize synchronization under varying frequency conditions, enabling reliable operation across a wide speed range.
2Measurement precision
If conventional phase matching techniques are used to correct phase shifts, then phase alignment is improved, but duty cycle distortions are not corrected leading to incomplete synchronization
Solution Approach 1:
The patent merges phase adjustment and duty cycle correction functions into a single edge phase mixing operation. By selectively phase-mixing specific edges of the internal clock signal with the external clock signal, the system simultaneously achieves both phase alignment and duty cycle correction, ensuring complete synchronization without requiring separate correction stages.
Solution Approach 2:
The patent uses the edge phase mixing unit as an intermediary mechanism that processes both phase and duty cycle characteristics of the clock signals. This intermediary selectively combines edges to produce an adjusted internal clock signal that satisfies both phase alignment and duty cycle requirements, achieving comprehensive synchronization correction.
3Measurement precision
If digital delay-locked loops are used to synchronize clock signals, then phase matching is improved, but circuit complexity and layout area increase significantly
Solution Approach 1:
The patent extracts only the essential phase and duty cycle correction functionality from complex delay-locked loop circuits. By implementing selective edge phase mixing with configurable mixing ratios, the system achieves the necessary synchronization precision without requiring the full complexity of DLL circuits, thereby reducing layout area and circuit complexity while maintaining adequate phase matching precision.
Data Source
AI summary
Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may operate to receive the clock signal and control signals. An output port of the selective edge phase mixing unit may be used to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.