Selective Edge Phase Mixing for High-Frequency Clock Synchronization
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Solution Overview
Problem
Synchronous integrated memory devices face challenges with phase shifts and duty cycle variations due to increased external clock frequencies, leading to synchronization issues and potential failure in memory operations.
Innovation Solution
A selective edge phase mixing apparatus and method that adjusts duty cycles by using a pair of serially-coupled NOT gates and pull-up/pull-down circuits to generate a clock signal with a desired duty cycle, utilizing AD and SD signals to dynamically or statically correct phase differences and duty cycle distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the external clock frequency is increased to improve processing speed, then the processing speed is improved, but phase shifts and duty cycle variations occur causing synchronization issues
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle distortion detection circuit continuously monitors the internal clock signal and generates correction signals (AD/SD) that are fed back to the edge phase mixing circuit. This closed-loop feedback system dynamically adjusts the clock signal parameters to compensate for phase shifts and duty cycle variations caused by high-frequency operation, thereby maintaining synchronization reliability while allowing high processing speeds
Solution Approach 2:
The patent changes the parameters of the clock signal by using the edge phase mixing circuit to dynamically adjust the duty cycle and phase of the internal clock signal. The correction signals modify the timing parameters of the clock edges, transforming the distorted clock signal into a synchronized one, thus resolving the contradiction between high speed operation and synchronization accuracy
2Reliability
If digital delay-locked loop circuitry is used to synchronize internal and external clock signals, then synchronization is improved, but the circuit occupies large layout area and introduces jitter
Solution Approach 1:
The patent extracts and eliminates the complex digital delay-locked loop circuitry from the memory device, replacing it with a simplified edge phase mixing circuit that performs the essential synchronization function. By removing the bulky DLL components while retaining the core clock synchronization capability through the edge phase mixing approach, the patent significantly reduces the circuit layout area while maintaining synchronization reliability
Solution Approach 2:
The patent uses a simplified model approach where the edge phase mixing circuit creates a corrected version of the clock signal based on detection of duty cycle distortions, rather than using the complex full-function DLL. This copying approach generates the necessary synchronized clock signal with fewer components, reducing area while achieving the same synchronization goal
3Measurement precision
If more gates are used to achieve desired synchronization, then synchronization precision is improved, but heat generation and jitter increase
Solution Approach 1:
The patent replaces the expensive, complex DLL circuitry with a simpler, more efficient edge phase mixing circuit that achieves synchronization with fewer gates. The simplified circuit generates less heat and introduces less jitter, effectively trading the complex high-precision DLL for a more efficient solution that meets synchronization requirements without the harmful side effects of heat and jitter
Data Source
AI summary
Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.