Selective EFU Task Offloading to ALUs for GPU Throughput
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Solution Overview
Problem
Existing graphical processing units (GPUs) face inefficiencies in throughput due to the imbalance between the number of elementary function units (EFUs) and arithmetic logical units (ALUs), limiting overall performance.
Innovation Solution
Selective offloading of EFU tasks to a plurality of ALUs, translating EFU native operations into ALU native operations to optimize GPU throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If EFU tasks are executed by dedicated EFUs, then operational precision is maintained, but GPU throughput is limited due to fewer EFUs compared to ALUs
Solution Approach 1:
The patent enables ALUs to perform both their native arithmetic operations and EFU operations by translating EFU native operations into equivalent ALU operation sequences. This multi-functionality allows the same hardware unit (ALU) to handle multiple types of operations, effectively increasing throughput without adding dedicated EFUs for every operation type.
Solution Approach 2:
The patent changes the operational parameters of ALUs by introducing translation mechanisms that convert EFU operation instructions into ALU operation sequences. This parameter transformation allows ALUs to execute EFU tasks by changing their operational mode from purely arithmetic to including specialized mathematical functions through instruction translation.
2Productivity
If more EFUs are added to increase throughput, then processing capacity improves, but device complexity and resource allocation efficiency deteriorate
Solution Approach 1:
Instead of adding more dedicated EFUs, the patent makes existing ALUs universal by enabling them to execute EFU operations through translation. This approach increases processing capacity for EFU tasks without increasing the total number of functional units, thereby avoiding the complexity and resource allocation issues that would arise from adding more specialized units.
Solution Approach 2:
The patent merges the functionality of separate EFUs and ALUs by allowing ALUs to perform both arithmetic operations and EFU operations. This consolidation reduces the overall number of functional units needed while maintaining or improving processing capacity, as ALUs can handle both types of operations through the translation mechanism.
3Productivity
If EFU operations are translated to ALU operations, then ALU utilization improves, but translation overhead increases
Solution Approach 1:
The translation of EFU operations to ALU operations is performed in advance during code compilation or instruction preparation, rather than being executed in real-time during runtime. This preliminary translation eliminates runtime overhead, as the translated ALU instruction sequences are ready for direct execution without additional translation delays during actual computation.
Data Source
AI summary
Aspects of the disclosure are directed to graphical processing unit (GPU) throughput by selective offloading of EFU tasks to a plurality of arithmetic logic units (ALUs). In accordance with one aspect, the disclosure includes receiving an elementary function unit (EFU) task with a sequence of elementary function unit (EFU) native operations in a graphical processing unit (GPU); and determining if the EFU task can be offloaded from a plurality of elementary function units (EFUs) in the GPU to a plurality of arithmetic logical units (ALUs) in the GPU according to a selection criterion.