Selective Epitaxial Fin Structure for Leakage and Latch-Up Control
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Solution Overview
Problem
As IC technologies progress towards smaller technology nodes, the increasing impedance between S/D epitaxial features and semiconductor substrate leads to higher latch-up impedance in well pick-up regions, degrading transistor performance in memory devices like SRAM arrays, despite efforts to stabilize well potential and uniform charge distribution.
Innovation Solution
Modifying S/D epitaxial features in well pick-up regions without an undoped epitaxial layer, while maintaining an undoped epitaxial layer in device regions to suppress leakage current, thereby improving latch-up performance without sacrificing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If an undoped epitaxial layer is added between S/D epitaxial features and substrate to suppress leakage current, then leakage current is reduced, but latch-up impedance increases in well pick-up regions
Solution Approach 1:
The patent applies different epitaxial layer configurations to different regions: device regions include an undoped epitaxial layer to suppress leakage current, while well pick-up regions exclude this layer to maintain low latch-up impedance. This spatial differentiation of structural properties resolves the contradiction by optimizing each region for its specific functional requirements.
2Productivity
If circuit geometry is scaled down to increase functional density, then production efficiency increases and costs decrease, but leakage between epitaxial features and substrate becomes more severe
Solution Approach 1:
The undoped epitaxial layer is selectively introduced in device regions where leakage suppression is critical, while maintaining standard structures in well pick-up regions. This localized modification enables continued scaling benefits while addressing leakage issues that arise at smaller geometries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances latch-up performance and maintains transistor efficiency by reducing leakage current, addressing the challenges of impedance and performance variability in advanced IC nodes.
Implementation Method 1
increasing impedance between S/D epitaxial features and semiconductor substrate leads to higher latch-up impedance
Data Source
AI summary
A method includes forming a first fin protruding from a substrate in a first region of the substrate and a second fin protruding from the substrate in a second region of the substrate, recessing a portion of the first fin, thereby forming a first recess, recessing a portion of the second fin, thereby forming a second recess, depositing a blocking layer in the second recess, growing a base epitaxial layer in the first recess, removing the blocking layer from the second recess, and growing a doped epitaxial layer in the first recess and the second recess. The base epitaxial layer is dopant free. The doped epitaxial layer abuts the first fin in the first region and the second fin in the second region.