Selective Epitaxial Growth for Gated Diode Leakage Reduction
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Solution Overview
Problem
As integrated circuits (ICs) miniaturize, short channel effects (SCEs) in planar transistors lead to increased current leakage, reduced threshold voltage, and degraded performance, particularly in gated diodes used for electrostatic discharge (ESD) protection, due to reduced channel lengths approaching depletion layer widths.
Innovation Solution
The selective use of epitaxial growth processes in the fabrication of gated diodes within ICs, where epitaxial growth is applied to fins of transistors in logic regions but not in I/O regions, allowing for reduced sub-threshold leakage current and improved performance by minimizing current leakage at pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length in planar transistors is reduced to increase drive strength and reduce parasitic capacitances, then drive current increases and circuit delay reduces, but short channel effects occur causing increased current leakage and reduced threshold voltage control
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures. By creating vertical fins that extend upward from the substrate, the gate can wrap around and control the channel from multiple directions, providing superior electrostatic control over the reduced channel length while maintaining high drive current through increased effective channel width.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by introducing fin height as a new dimension. The fin height is controlled to be between 5-20 nm, creating a vertical channel that increases the effective gate control area without increasing the planar footprint, thereby improving threshold voltage control while maintaining small channel length.
2Device complexity
If the same fabrication processes are used for both FETs and gated diodes throughout the IC, then manufacturing complexity is reduced, but sub-threshold leakage current increases in gated diodes particularly in I/O regions
Solution Approach 1:
The patent applies different epitaxial growth conditions to different regions of the IC. I/O region gated diodes are fabricated without epitaxial growth to minimize sub-threshold leakage current, while logic region devices use epitaxial growth for optimized performance. This local differentiation allows each region to have tailored properties suited to its specific functional requirements.
Solution Approach 2:
The patent segments the IC into distinct fabrication zones: I/O regions where gated diodes are formed without epitaxial growth, and logic regions where devices are formed with epitaxial growth. Mask patterns and process parameters are adjusted locally for each segment, allowing independent optimization of leakage current in I/O regions while maintaining performance in logic regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces sub-threshold leakage current in I/O regions, enhancing the overall performance of ICs by maintaining better control over electrostatic discharge and reducing parasitic capacitances, thus improving the reliability of ESD protection circuits.
Implementation Method 1
fins are fabricated, in part, using an epitaxial growth process
Data Source
AI summary
An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.