Selective Epitaxial Germanium Buffer for FinFET Channel Uniformity
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Solution Overview
Problem
Integrating germanium into the channel region of FinFET devices for improved charge carrier mobility is challenging due to difficulties in filling narrow trenches with epitaxial material and achieving uniform buffer recess control, leading to suboptimal channel height uniformity in CMOS devices.
Innovation Solution
A method involving selective epitaxial processes to form silicon-germanium layers over silicon substrates, using a buffer layer with varying germanium content, and forming fins with precise gap control between features, along with insulating material deposition at low temperatures, to fabricate CMOS FinFET devices with uniform channel heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If aspect ratio trapping is used to reduce defects in shallow trench isolation, then device reliability is improved, but manufacturing complexity increases due to the difficulty of filling narrow trenches with epitaxial material
Solution Approach 1:
The patent applies local quality by creating separate epitaxial growth regions for NMOS and PMOS devices with different germanium concentrations. The buffer layer has a graded composition (Si1-xGex where x ranges from 0 to 0.8) that varies locally to match the specific requirements of each device type, enabling defect reduction without requiring complex trench filling processes
Solution Approach 2:
The invention segments the epitaxial growth process into distinct stages: first forming a buffer layer with graded germanium content, then separately forming NMOS features and PMOS features with their respective germanium concentrations. This segmentation allows each region to be optimized independently, improving reliability while simplifying manufacturing compared to attempting to fill narrow trenches
2Reliability
If germanium is included in the channel region to increase charge carrier mobility, then device performance is improved, but manufacturing precision deteriorates due to difficulties in achieving uniform buffer recess control
Solution Approach 1:
The patent applies preliminary action by first forming a buffer layer with graded germanium content before forming the actual device features. This pre-formed buffer layer establishes a controlled foundation that enables subsequent epitaxial growth to achieve uniform channel heights, preventing the manufacturing precision issues that would otherwise occur when directly forming features with high germanium content
Solution Approach 2:
The invention uses parameter changes by varying the germanium concentration in the buffer layer (Si1-xGex where x ranges from 0 to 0.8) to control epitaxial growth characteristics. By adjusting this composition parameter across different regions and growth stages, the patent achieves both high device performance from germanium inclusion and uniform channel height control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables the formation of CMOS FinFET devices with improved channel mobility and reduced leakage current, enhancing switching speeds and reducing power consumption by achieving uniform channel heights and effective integration of germanium in both n-channel and p-channel MOS devices.
Implementation Method 1
using a first selective epitaxial process to form a first feature comprising silicon—e.g., Si1−zGez, where z ranges from 0 to about 0.7 (e.g., for an NMOS device)—overlying the buffer layer on a surface, and using a second selective epitaxial process to form a second feature comprising Si1−yGey
Implementation Method 2
forming a buffer layer comprising Si1−xGex, where x ranges from 0 to about 0.8 or 0 to about 0.5, overlying the substrate
Data Source
AI summary
Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both n-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.