Selective Epitaxial Growth for Co-Integrated N and P Type Fin Structures

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Solution Overview

Problem

Current methods fail to efficiently and reliably co-integrate n- and p-type MOS material epitaxial growths on a single Silicon substrate due to large lattice mismatches, leading to defects in fin-based circuit devices, which affect performance and yield.

Innovation Solution

The process involves forming trenches with aspect ratios where the height is greater than or equal to 1.5 times the width and length, trapping defects along the sidewalls of shallow trench isolation (STI) regions, and using selective epitaxial growth to form p- and n-type epitaxial device fins from the same substrate, reducing crystaline defects and enabling simultaneous integration of n- and p-type MOS devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If lattice mismatched materials (III-V, Ge) are grown on Silicon substrate, then carrier mobility and device performance are improved, but crystaline defects are generated due to large lattice mismatch

Engineering Contradiction:
Improvedevice performanceVSAvoidcrystaline defects
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A buffer layer is introduced as an intermediary between the Silicon substrate and the III-V or Ge epitaxial layers. This buffer layer acts as a mediator that accommodates the lattice mismatch, preventing defect propagation to the active device regions while enabling the growth of high-quality epitaxial layers for improved carrier mobility

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The epitaxial structure is segmented into distinct functional layers: a buffer layer for defect management, and separate active device regions for n-type and p-type MOSFETs. This segmentation isolates the defect-prone buffer region from the high-performance active regions, allowing each to optimize its function

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If conventional epitaxial growth is used on Silicon substrate, then manufacturing process is simple, but co-integration of n- and p-type MOS materials is not achieved

Engineering Contradiction:
Improveprocess simplicityVSAvoidco-integration capability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

Different epitaxial materials are grown in locally defined regions of the substrate. n-type MOSFETs are formed in first and second epitaxial regions, while p-type MOSFETs are formed in a third epitaxial region. This local differentiation enables co-integration of complementary devices on a single Silicon substrate while maintaining process compatibility

Inventive Principle:
Principle #3Local quality

3Loss of substance

If trenches with small aspect ratio are used, then material usage is reduced, but defect trapping efficiency is insufficient

Engineering Contradiction:
Improvematerial usageVSAvoiddefect trapping efficiency
Core Design Contradiction:
Loss of substanceVSReliability

Solution Approach 1:

The trench aspect ratio is optimized to a minimum of 1.5:1 (height to width), representing a critical parameter threshold that simultaneously achieves effective defect trapping and reasonable material consumption. This parameter optimization balances the competing requirements of defect management and material efficiency

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces defects in fin-based devices, enhances the reliability of forming both n- and p-type epitaxial device fins, and allows for thicker, shorter trenches, improving crystal quality and yield while minimizing material usage.

Implementation Method 1

simultaneously epitaxially growing a first and second epitaxial region of a first type of epitaxial material on a substrate surface

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

trapping defects along the sidewalls of shallow trench isolation (STI) regions

Methodology Applied
Scientific EffectDefect trapping: Gettering

Data Source

PatentUS9685381B2Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon
Publication Date: 2017.06.20 INTEL CORP
  • US9685381B2 patent drawing
  • US9685381B2 patent drawing
  • US9685381B2 patent drawing

AI summary

Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.