Selective Erase Control for Memory Cell Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices lack the ability to selectively erase memory cells without affecting unselected cells, leading to reduced reliability due to overlapping threshold voltages during erase operations.
Innovation Solution
A memory device with a memory block and peripheral circuit capable of performing selective erase operations by applying specific voltages to selected word lines and strings while floating unselected ones, preventing unselected memory cells from being erased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional erase operation is performed on memory blocks, then all memory cells are erased, but unselected memory cells are also affected causing threshold voltage overlap and reduced reliability
Solution Approach 1:
The memory block is segmented into selected and unselected regions through independent voltage control of word lines and strings. The control logic applies erase voltage only to selected word lines and selected strings, while floating unselected word lines and unselected strings, thereby segmenting the erase operation spatially within the memory block.
Solution Approach 2:
Different voltage conditions are applied to different regions of the memory block. Selected word lines receive erase allowable voltage and selected strings receive erase voltage, while unselected word lines and unselected strings are floated. This local differentiation ensures that only specific memory cells undergo erasure, preserving the integrity of unselected cells.
2Measurement precision
If erase voltage is applied to all strings, then erase operation is simple to perform, but unselected memory cells are inadvertently erased reducing precision
Solution Approach 1:
The voltage control system dynamically adjusts the electrical state of word lines and strings based on selection status. The control logic enables or disables voltage application to specific word lines and strings according to the erase operation requirements, providing dynamic adaptability between different erase scenarios (full block erase vs. selective erase).
Solution Approach 2:
The control logic acts as an intermediary between the erase command and the voltage application mechanism. It processes the erase command and generates appropriate control signals to enable selective voltage application to word lines and strings, mediating the complex voltage control requirements.
3Reliability
If floating unselected word lines and strings is implemented, then selective erase precision is improved, but control circuit complexity increases
Solution Approach 1:
The control logic is designed to handle multiple operations (read, program, erase, selective erase) using a unified voltage control framework. The same control logic that manages standard erase operations also manages selective erase operations by selectively enabling or disabling voltage application to specific word lines and strings, reducing the need for separate dedicated control circuits.
Data Source
AI summary
Provided herein may be a memory device and a memory system including the memory device. The memory device may include a memory block including a plurality of memory cells, a peripheral circuit configured to perform a selective erase operation on the memory cells, and control logic configured to control, during the selective erase operation, the peripheral circuit to apply an erase allowable voltage to a selected word line among a plurality of word lines in the memory block, apply an erase voltage to a selected string among a plurality of strings in the memory block, and float unselected word lines and unselected strings.