Selective Etch Stop Layers for Low-Capacitance Transistor Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing transistor manufacturing processes face challenges in reducing parasitic capacitance and contact plug resistance due to the formation of etch stop layers that are not selectively controlled, leading to inefficiencies in integrated circuit performance.
Innovation Solution
The selective formation of etch stop layers on conductive features, such as source/drain regions and contact plugs, while avoiding dielectric regions, reduces parasitic capacitance and contact plug resistance by using inhibitor films and etch stop layers with higher dielectric constants, thereby optimizing the structure for reduced sizes and improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etch stop layers are formed on all regions including dielectric regions, then the etching process is simplified and more uniform, but parasitic capacitance increases and contact plug resistance increases
Solution Approach 1:
The patent applies local quality by selectively forming etch stop layers only on conductive features (source/drain regions and contact plugs) while excluding dielectric regions. This is achieved through a two-step process: first forming an inhibitor film on dielectric regions, then depositing the etch stop layer which adheres only to conductive features where the inhibitor film is absent. This selective approach reduces parasitic capacitance by eliminating etch stop layers from dielectric regions while maintaining etching uniformity on conductive features.
2Ease of manufacture
If etch stop layers are formed on all regions including dielectric regions, then the etching process is simplified and more uniform, but contact plug resistance increases
Solution Approach 1:
The patent applies local quality by selectively forming etch stop layers only on conductive features (source/drain regions and contact plugs) while excluding dielectric regions. This is achieved through a two-step process: first forming an inhibitor film on dielectric regions, then depositing the etch stop layer which adheres only to conductive features where the inhibitor film is absent. This selective approach reduces contact plug resistance by eliminating unnecessary etch stop layers from dielectric regions while maintaining etching uniformity on conductive features.
3Object-affected harmful factors
If etch stop layers are selectively formed on conductive features only, then parasitic capacitance is reduced and contact plug resistance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent uses an inhibitor film as an intermediary layer to enable selective formation of etch stop layers. The inhibitor film is first deposited on dielectric regions, then the etch stop layer is deposited which adheres only to conductive features where the inhibitor film is absent. After etching, the inhibitor film is removed. This intermediary approach adds only one or two process steps while achieving the desired selectivity, making the complexity increase manageable compared to the benefits of reduced parasitic capacitance and contact plug resistance.
4Reliability
If etch stop layers are selectively formed on conductive features only, then parasitic capacitance is reduced and contact plug resistance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent uses an inhibitor film as an intermediary layer to enable selective formation of etch stop layers. The inhibitor film is first deposited on dielectric regions, then the etch stop layer is deposited which adheres only to conductive features where the inhibitor film is absent. After etching, the inhibitor film is removed. This intermediary approach adds only one or two process steps while achieving the desired selectivity, making the complexity increase manageable compared to the benefits of reduced contact plug resistance and parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes parasitic capacitance and contact plug resistance, enhancing the performance of transistors like FinFETs and GAA transistors by providing wider contact plugs and lower parasitic capacitance, thus improving the overall efficiency and functionality of integrated circuits.
Implementation Method 1
forming a source/drain contact plug over and electrically coupling to the source/drain region; forming a gate contact plug over and electrically coupling to the gate stack; selectively forming a first inhibitor film on a dielectric layer nearby a conductive feature, wherein the conductive feature is selected from the group consisting of the source/drain region, the source/drain contact plug, and the gate contact plug; selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon
Implementation Method 2
selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon; The selective formation of etch stop layers on conductive features, such as source/drain regions and contact plugs, while avoiding dielectric regions, reduces parasitic capacitance and contact plug resistance by using inhibitor films and etch stop layers with higher dielectric constants
Data Source
AI summary
A method comprises forming a gate stack over a semiconductor region, performing an epitaxy process to form a source/drain region aside of the gate stack, forming a source/drain contact plug over and electrically coupling to the source/drain region, forming a gate contact plug over and electrically coupling to the gate stack, and selectively forming an inhibitor film on a dielectric layer nearby a conductive feature. The conductive feature is selected from the group consisting of the source/drain region, the source/drain contact plug, and the gate contact plug. An etch stop layer is selectively deposited on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon. The inhibitor film is then removed.