Selective Etch Stop Layer Placement for Lower FinFET Contact Parasitics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the formation of FinFETs and GAA transistors, existing technologies face challenges in reducing parasitic capacitance and contact plug resistance due to the size and placement of etch stop layers.
Innovation Solution
The solution involves selectively forming inhibitor films on dielectric regions and using these films to prevent the formation of etch stop layers in certain areas, thereby reducing the size of the etch stop layers and minimizing parasitic capacitance. This approach also allows for wider contact plugs, reducing their resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If etch stop layers are formed on all dielectric regions, then the etch stop layers provide comprehensive protection during subsequent etching processes, but the parasitic capacitance between conductive features increases
Solution Approach 1:
The patent applies local quality by selectively forming etch stop layers only on specific dielectric regions (such as shallow trench isolation regions) while omitting them from other dielectric regions (such as inter-layer dielectric regions). This localized approach provides etch stop protection exactly where needed during contact hole etching while minimizing the overall capacitance contribution from etch stop layers, thereby resolving the contradiction between comprehensive protection and parasitic capacitance reduction.
2Reliability
If etch stop layers are formed in all areas, then the etching process is protected from damaging underlying structures, but the contact plug resistance increases due to narrower contact plugs
Solution Approach 1:
The patent implements local quality by spatially differentiating the formation of etch stop layers across different dielectric regions. Etch stop layers are formed on shallow trench isolation regions to protect underlying structures during etching, while being omitted from inter-layer dielectric regions to allow wider contact plugs. This selective approach maintains etching protection where structurally necessary while minimizing resistance where electrical connectivity is prioritized.
Solution Approach 2:
The patent applies segmentation by dividing the dielectric regions into distinct zones with different etch stop layer configurations. The substrate is segmented into regions requiring etch protection (STI regions overlying semiconductor fins) and regions where electrical performance is prioritized (ILD regions between conductive features). This segmentation allows the etching process to be protected in critical areas while enabling lower resistance contact plugs in non-critical areas.
3Reliability
If the size of etch stop layers is increased, then the etch stop layers provide more robust protection during etching, but the parasitic capacitance between conductive features increases
Solution Approach 1:
The patent applies local quality by controlling the spatial distribution and dimensions of etch stop layers. Etch stop layers are formed with sufficient size and thickness on shallow trench isolation regions to provide robust protection during contact hole etching processes. Conversely, etch stop layers are omitted from inter-layer dielectric regions, eliminating their capacitance contribution entirely. This localized size control ensures robust protection where needed while minimizing parasitic capacitance where conductive features are present.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
By reducing the size of etch stop layers and optimizing their placement, the parasitic capacitance between conductive features is decreased, and the resistance of contact plugs is lowered, leading to improved performance in FinFETs and GAA transistors.
Implementation Method 1
selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon
Data Source
AI summary
A method comprises forming a gate stack over a semiconductor region, performing an epitaxy process to form a source/drain region aside of the gate stack, forming a source/drain contact plug over and electrically coupling to the source/drain region, forming a gate contact plug over and electrically coupling to the gate stack, and selectively forming an inhibitor film on a dielectric layer nearby a conductive feature. The conductive feature is selected from the group consisting of the source/drain region, the source/drain contact plug, and the gate contact plug. An etch stop layer is selectively deposited on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon. The inhibitor film is then removed.