Selective Fin Thinning for Semiconductor Logic and Memory Integration
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Solution Overview
Problem
Current methods for manufacturing semiconductor devices with fin-type MISFETs in both memory cell and logic portions face challenges in achieving stable and precise fin formation, particularly in controlling the width and etching variations, which affect the reliability and miniaturization of the devices.
Innovation Solution
A method involving the formation of fins with different widths in the memory cell and logic portions using a combination of anisotropic and isotropic etching techniques, where the fins in the logic portion are selectively thinned to achieve a narrower width, reducing etching variations and improving processing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form fins in both memory cell and logic portions, then the manufacturing process is simple, but the fin width control precision and etching variation are poor
Solution Approach 1:
The etching process is segmented into two distinct stages: a first etching process that forms fins with a preliminary width, and a second etching process that selectively thins fins in the logic portion. This segmentation allows each etching step to be optimized independently, achieving precise fin width control without requiring an entirely complex new process
Solution Approach 2:
The patent applies different etching conditions to different regions: the first etching process treats both memory cell and logic portion fins uniformly, while the second etching process selectively thins only the logic portion fins. This local differentiation enables precise width control for each region according to its specific requirements
2Productivity
If fins with uniform width are formed in both memory cell and logic portions, then the manufacturing process is straightforward, but the logic portion performance and miniaturization are limited
Solution Approach 1:
The patent creates fins with different widths in different regions by applying a second etching process selectively to the logic portion. This allows the logic portion fins to be thinner for better miniaturization and performance, while memory cell fins maintain their original width for reliable operation
Solution Approach 2:
The first etching process performs a preliminary fin formation step that creates fins with a standard width suitable for memory cells. This preliminary structure serves as a base that can then be selectively modified in the logic portion through the second etching process
3Manufacturing precision
If a single etching process is used for fin formation, then the manufacturing yield is maintained, but the etching variation and fin dimension control are insufficient
Solution Approach 1:
The patent divides fin formation into two etching steps with different purposes: the first step establishes the base fin structure with controlled width, and the second step performs selective thinning in the logic portion. This segmentation reduces etching variation by optimizing each step independently
Solution Approach 2:
The two-step etching process provides implicit feedback control: the first etching process establishes a reference fin width, and the second process adjusts the logic portion fin width based on the actual results of the first process, compensating for etching variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturing yield and reduces defects, allowing for more precise control over fin dimensions, thereby improving the performance and integration of the logic portion while maintaining the reliability of the memory cell portion.
Implementation Method 1
forming a first convex portion under the second mask film by providing concave portions through etching of parts of the semiconductor substrate located outside the second mask films
Implementation Method 2
Japanese Unexamined Patent Application Publication No. 2013-98192 (Patent Document 2) discloses a technique that uses isotropic etching to shorten the length of a sidewall
Data Source
AI summary
Provided is a stable manufacturing method for a semiconductor device. In the manufacturing method for a semiconductor device, first, fins with an equal width are formed in each of a memory cell portion and a logic portion of a semiconductor substrate. Then, the fins in the logic portion are etched with the fins in the memory cell covered with a mask film, thereby fabricating fins in the logic portion, each of which is narrower than the fin formed in the memory cell portion.