Selective Fuse Programming for Semiconductor Memory Repair

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Solution Overview

Problem

Existing semiconductor circuits cannot selectively perform fuse programming on specific memory chips within a configured memory module, making it impossible to repair individual memory chips after the module is set up.

Innovation Solution

A semiconductor memory apparatus and system that includes a core block for data storage, a control unit to activate a control signal in response to a test mode signal and a command, and a fuse circuit for selective programming, allowing a memory controller to identify and repair failed memory chips by inputting predetermined data values and commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fuse programming is performed before memory module configuration, then single bit fail can be repaired, but selective repair of individual memory chips after configuration is not possible

Engineering Contradiction:
Improvesingle bit fail repair capabilityVSAvoidselective programming capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic control of fuse programming by enabling the operation to be performed either before or after memory module configuration based on system needs. The memory controller dynamically selects the programming timing and targets specific memory chips within the module after configuration, making the system adaptable to different repair scenarios.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent divides the memory module into individually addressable memory chips, allowing selective fuse programming of specific chips rather than requiring programming of all chips in the module. This segmentation enables targeted repair of failed chips while leaving other chips operational.

Inventive Principle:
Principle #1Segmentation

2Reliability

If fuse programming is performed on all memory chips, then all potential fails can be addressed, but individual chip selection and targeted repair becomes impossible

Engineering Contradiction:
Improvefail repair coverageVSAvoidindividual chip selection
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent applies local quality by enabling fuse programming to be performed on specific memory chips within the module based on their individual needs. The memory controller can identify which chips have failures and apply programming only to those specific chips, rather than uniformly programming all chips in the module.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The memory controller acts as an intermediary that receives failure information, identifies specific memory chips requiring repair, and selectively activates fuse programming for those chips. This intermediary function enables targeted repair operations without affecting other chips in the module.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If memory module is configured with multiple semiconductor memories, then system capacity increases, but the ability to select and repair specific failed chips is lost

Engineering Contradiction:
Improvememory capacityVSAvoidselective chip repair
Core Design Contradiction:
Quantity of substanceVSEase of repair

Solution Approach 1:

The patent maintains the segmented structure of multiple semiconductor memories within the module while adding the capability to individually address and repair specific chips. Each memory chip retains its identity and can be independently selected for fuse programming based on failure detection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements feedback by testing memory chips to detect failures, then using this information to selectively program only the chips that require repair. The memory controller receives feedback about chip status and adjusts programming operations accordingly, enabling easy repair of specific failed chips in multi-chip modules.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8437212B2Semiconductor memory apparatus, memory system, and programming method thereof
Publication Date: 2013.05.07 SK HYNIX INC
  • US8437212B2 patent drawing
  • US8437212B2 patent drawing
  • US8437212B2 patent drawing

AI summary

Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus includes a core block configured to receive and store external input data, a control unit configured to activate a control signal in response to a test mode signal and a command, when the external input data has a predetermined value, and a fuse circuit configured to perform fuse programming when the control signal is activated.