Selective GAA Gate Structures for Ultra-Low Threshold FETs
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down metal oxide semiconductor field effect transistors (MOSFETs) to achieve ultra-low threshold voltages while maintaining manufacturing complexity and cost-effectiveness, particularly in forming gate structures with nanostructured channel regions that require precise control of work function values and layer thicknesses.
Innovation Solution
The development of gate structures for finFETs and gate-all-around (GAA) FETs with Al-based n-type work function metal layers and Al-free p-type work function metal bi-layers, along with selective formation of Si capping layers, allows for the achievement of ultra-low threshold voltages by optimizing the thickness and material composition of gate stack layers, enabling the formation of FETs with different conductivity types on the same substrate with reduced complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of work function metal (WFM) layers is increased to achieve ultra-low threshold voltage, then the threshold voltage is reduced, but the gate stack thickness increases and manufacturing complexity increases
Solution Approach 1:
The WFM layer is segmented into multiple sub-layers with different materials and thicknesses. For n-type FETs, the WFM layer includes a first sub-layer (e.g., TiAlN) and a second sub-layer (e.g., Al-doped TiN). For p-type FETs, the WFM layer includes a first sub-layer (e.g., TiN) and a second sub-layer (e.g., TaN). This segmentation allows optimization of each sub-layer's properties to achieve ultra-low threshold voltage without requiring excessive total thickness.
Solution Approach 2:
The patent employs composite material structures for the WFM layers, combining different metal and metal nitride materials in specific sequences. The composite structure leverages the work function characteristics of each material to achieve the desired threshold voltage. For example, Al-based materials provide lower work function for n-type FETs, while TiN and TaN provide appropriate work functions for p-type FETs.
2Reliability
If the thickness of WFM layers is increased to achieve ultra-low threshold voltage, then the threshold voltage is reduced, but the deposition process becomes more complex and costly
Solution Approach 1:
The deposition process is segmented into multiple sequential steps, depositing one WFM sub-layer after another. Each sub-layer is deposited with controlled thickness and composition, allowing precise control over the final work function characteristics. This segmented approach simplifies the overall process compared to attempting to deposit a single thick layer with uniform properties.
Solution Approach 2:
The patent utilizes parameter changes during deposition, including variations in deposition temperature, pressure, and material composition ratios, to achieve the desired WFM layer properties. By adjusting these parameters between sub-layer deposits, the process achieves precise control over work function while maintaining manufacturability.
3Productivity
If the gate stack thickness is reduced to improve manufacturing efficiency, then the gate stack becomes thinner, but achieving ultra-low threshold voltage becomes more difficult
Solution Approach 1:
The composite WFM layer structure enables achieving ultra-low threshold voltage with reduced total thickness by optimizing the work function contribution of each material layer. The combination of Al-based materials in n-type FETs and TiN/TaN materials in p-type FETs provides high work function modulation efficiency, allowing thinner stacks to achieve the same voltage reduction.
Solution Approach 2:
Different regions of the gate stack have optimized local compositions and thicknesses. The WFM sub-layers are designed with specific thicknesses and material compositions tailored to their local function within the stack. This local optimization allows the overall stack to be thinner while maintaining the capability to achieve ultra-low threshold voltage.
Data Source
AI summary
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.