Selective Gain Control Circuit for CMOS Image Sensor FPN
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Solution Overview
Problem
Conventional methods for reducing column fixed pattern noise (FPN) in CMOS image sensors, such as correlated double sampling, are limited by non-linearity and variation of column sampling circuits, leading to residual FPN due to capacitor mismatch-induced gain errors, which become more significant as pixel size decreases.
Innovation Solution
The implementation of a gain control circuit with a configurable feedback mechanism that selectively includes or excludes parallel legs to achieve substantially equal loop gains, reducing FPN by varying the feedback capacitance across an amplifier, thereby averaging out variations in semiconductor fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixel cell size is decreased to achieve higher resolution, then image quality improves, but capacitor mismatch-induced gain error increases
Solution Approach 1:
The feedback network is divided into multiple parallel legs (first leg, second leg, third leg, fourth leg), each containing switches and capacitors. By selectively enabling different combinations of these legs, the circuit achieves multiple gain settings while distributing the capacitive load across multiple components, thereby reducing the impact of individual capacitor mismatches on overall gain accuracy.
Solution Approach 2:
The circuit dynamically changes the feedback capacitance value by selectively switching different capacitor combinations in parallel legs. This allows the gain to be adjusted according to lighting conditions while maintaining consistent loop gain through coordinated switching of multiple legs, compensating for capacitor mismatch effects.
2Object-affected harmful factors
If correlated double sampling is used to reduce column FPN, then noise reduction is achieved, but residual FPN remains due to non-linearity and variation of column sampling circuits
Solution Approach 1:
The patent implements a feedback mechanism where the output of the amplifier is fed back through a configurable network of switches and capacitors to the input. This feedback loop dynamically adjusts the gain to maintain consistent loop gain across different operating conditions, thereby reducing residual FPN that persists after correlated double sampling.
Solution Approach 2:
The feedback network is made dynamic through the use of switches that can selectively connect different capacitor combinations. This allows the circuit to adapt its gain setting in real-time based on signal conditions, maintaining optimal performance and reducing residual noise across varying illumination levels.
3Object-affected harmful factors
If feedback capacitance is varied across the amplifier to reduce FPN, then noise reduction is achieved, but device complexity increases
Solution Approach 1:
The feedback network is segmented into multiple parallel legs with switches and capacitors in each leg. This segmentation allows the complex function of variable gain control to be distributed across multiple simple, identical building blocks, making the overall complex function manageable and implementable with standardized circuit elements.
Solution Approach 2:
Each leg in the feedback network serves multiple functions: it provides feedback capacitance, enables gain control, and contributes to maintaining consistent loop gain. The switches within each leg can selectively connect or disconnect capacitors to achieve different gain settings, making the same structural elements serve multiple purposes and reducing overall circuit complexity.
Data Source
AI summary
A circuit for providing signal amplification with reduced fixed pattern noise. In an embodiment, the circuit includes an amplifier and a plurality of legs coupled in parallel with one another between a first node for an input of the amplifier and a second node for an output of the amplifier. Control logic selects a first combination of the plurality of legs for a first configuration of the circuit to provide a first loop gain with the amplifier. In another embodiment, the control logic further selects a second combination of the plurality of legs for a second configuration of the circuit to provide a second loop gain with the amplifier, wherein the first loop gain is substantially equal to the second loop gain.