Selective Metal Caps on Gate Electrodes to Cut Gate Resistance
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Solution Overview
Problem
As semiconductor devices continue to scale down, gate resistance increases, adversely impacting device performance such as speed.
Innovation Solution
The method involves depositing an n-type work function layer over a gate dielectric layer, forming a dielectric capping layer to prevent oxidation, and selectively forming metal caps directly on the p-type and n-type work function layers without covering the gate dielectric or capping layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is scaled down to increase functional density, then production efficiency and cost are improved, but gate resistance increases and device performance deteriorates
Solution Approach 1:
The patent applies local quality by forming metal caps selectively at specific locations (gate contacts and gate electrode regions) rather than uniformly across the entire structure. The metal caps are deposited only where needed to reduce gate resistance, while leaving other regions unchanged. This localized modification allows performance improvement without requiring global structural changes, thus maintaining productivity benefits of scaling while addressing the gate resistance issue in critical areas.
2Reliability
If metal caps are formed to reduce gate resistance, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs self-service through selective deposition processes where the metal cap material automatically deposits only on desired surfaces (gate contacts and gate electrodes) due to surface chemistry differences. The deposition process itself provides the selectivity without requiring additional masking or patterning steps. This self-selective behavior simplifies manufacturing by eliminating complex alignment and patterning operations that would otherwise be needed to place metal caps only where required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate resistance, particularly in n-type transistors, thereby enhancing the overall performance of semiconductor structures.
Implementation Method 1
depositing an n-type work function layer over a gate dielectric layer
Implementation Method 2
forming a dielectric capping layer to prevent oxidation
Implementation Method 3
selectively forming metal caps directly on the p-type and n-type work function layers
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.