Selective Gate Dielectric Deposition to Cut Parasitic Capacitance
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Solution Overview
Problem
The increasing parasitic capacitance between conductive elements in integrated circuits due to shrinking critical dimensions leads to significant resistance-capacitance (RC) time delay, which affects device performance.
Innovation Solution
A method for selectively depositing a high-k dielectric layer on an interfacial layer of a transistor while leaving gate spacers exposed, reducing parasitic capacitance by eliminating the dielectric material between the gate electrode and source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a dielectric layer is formed on all surfaces including gate spacers, then the manufacturing process is simple and continuous, but parasitic capacitance between gate electrode and source/drain contacts increases
Solution Approach 1:
The patent applies local quality by treating different surfaces differently: the interfacial layer is activated to receive dielectric material while gate spacer surfaces are passivated with monolayers to repel dielectric material. This selective surface treatment ensures the dielectric layer is formed only where needed (on the interfacial layer) and not where it would create harmful parasitic capacitance (on gate spacers adjacent to source/drain contacts).
Solution Approach 2:
The patent uses self-assembled monolayers as intermediary substances on the gate spacer surfaces. These monolayers act as mediators that prevent direct interaction between the dielectric precursor and the gate spacer surface, thereby blocking unwanted dielectric deposition. The monolayers are temporarily introduced and subsequently removed after serving their protective function.
2Productivity
If the critical dimension of transistors is shrunk to increase integration density, then more transistors can be packed, but parasitic capacitance between conductive elements increases leading to RC delay
Solution Approach 1:
The patent extracts the harmful dielectric material from specific locations where it creates parasitic capacitance. By selectively preventing dielectric deposition on gate spacer surfaces adjacent to source/drain contacts, the invention removes the source of parasitic capacitance while maintaining the dielectric layer in locations where it provides necessary electrical isolation and device functionality.
3Device complexity
If dielectric material is deposited uniformly across all surfaces, then deposition control is simple, but selective coverage of interfacial layer versus gate spacers cannot be achieved
Solution Approach 1:
The patent changes the surface chemical parameters of different substrates (interfacial layer vs. gate spacers) to achieve selective deposition. By modifying the surface energy and chemical reactivity through monolayer formation, the dielectric precursor exhibits different deposition behavior on different surfaces, enabling precise spatial control over where the dielectric layer forms without complex deposition process adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces RC delay by minimizing parasitic capacitance, thereby enhancing the performance of semiconductor structures such as planar FETs, FinFETs, and GAAFETs.
Implementation Method 1
selectively forming a first self-assembled monolayer on the first surface of the interfacial layer while leaving the two second surfaces of the two dielectric spacers exposed from the first self-assembled monolayer
Implementation Method 2
selectively forming a gate dielectric layer on the first surface of the interfacial layer while leaving the two second self-assembled monolayers exposed from the gate dielectric layer
Implementation Method 3
selectively forming a gate dielectric layer on the first surface of the interfacial layer
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: forming a patterned structure including an interfacial layer and two dielectric spacers, a first surface of the interfacial layer and two second surfaces of the two dielectric spacers being arranged to border a cavity, the first surface being formed with first functional groups, the two second surfaces being formed with second functional groups; selectively forming a first self-assembled monolayer on the first surface of the interfacial layer; selectively forming two dummy layers respectively on the two second surfaces of the two dielectric spacers; removing the first self-assembled monolayer to expose the first surface of the interfacial layer; selectively forming two second self-assembled monolayers respectively on the two dummy layers; and selectively forming a gate dielectric layer on the first surface of the interfacial layer.