Selective Gate Dielectric Deposition for Low-RC Nanosheet Gates
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Solution Overview
Problem
As feature sizes in semiconductor devices decrease, the distance between metal features reduces, leading to increased resistance and parasitic capacitance, resulting in larger resistance-capacitance (RC) time delay.
Innovation Solution
A selective deposition process is used to form a gate dielectric layer that avoids deposition on sidewall spacers, employing a self-assembled monolayer formed by an azidation and click reaction to block nitrogen-containing spacers, allowing a metal filling layer to be in direct contact with the spacers without a high-k dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-k dielectric material is globally deposited to form a gate dielectric layer, then the gate dielectric is formed, but the dielectric layer laterally covers sidewall spacers resulting in increased parasitic capacitance and larger RC time delay
Solution Approach 1:
The patent applies local quality by making the sidewall spacers have different properties than the channel region. Specifically, the sidewall spacers are formed with a material composition or structure that prevents high-k dielectric material deposition, creating a localized difference in dielectric properties. This selective local modification allows the gate dielectric to be formed on the channel while avoiding deposition on the sidewall spacers, thereby reducing parasitic capacitance without compromising gate dielectric formation.
2Productivity
If feature sizes are decreased to improve integration density, then integration density is improved, but the distance between metal features reduces leading to increased resistance and parasitic capacitance
Solution Approach 1:
The patent uses local quality to create specific regions with different electrical properties. By modifying the sidewall spacer regions to have different dielectric characteristics compared to the channel region, the invention locally reduces parasitic capacitance at critical interfaces. This localized modification allows continued scaling of feature sizes for improved integration density while mitigating the harmful effects of increased resistance and parasitic capacitance that would normally result from reduced spacing between metal features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and RC time delay, enhancing the performance of semiconductor devices by minimizing the formation of high-k dielectric material on sidewall spacers.
Implementation Method 1
employing a self-assembled monolayer formed by an azidation and click reaction to block nitrogen-containing spacers
Implementation Method 2
employing a self-assembled monolayer formed by an azidation and click reaction to block nitrogen-containing spacers
Implementation Method 3
employing a self-assembled monolayer formed by an azidation and click reaction to block nitrogen-containing spacers
Data Source
AI summary
A method for manufacturing a semiconductor device includes: forming a semiconductor structure on a substrate; forming a blocking layer to cover side surfaces of spacers of the semiconductor structure by subjecting a nitrogen-containing dielectric material of the spacers to an azidation reaction with an azide compound and a click reaction with a plurality of precursor molecules, each of which includes a head group containing an alkyne radical and a tail group connected to the head group; forming a gate dielectric layer surrounding nanosheet segments of the semiconductor structure; removing the blocking layer; and forming a metal filling layer which is in direct contact with the spacers, and which surrounds the nanosheet segments and is separated from the nanosheet segments by the gate dielectric layer.