Selective Gate Dielectric Deposition for FinFET and GAA Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing advanced integrated circuits due to the increasing complexity of processing and manufacturing as transistors are scaled down, requiring innovative solutions for efficient production.
Innovation Solution
The development of FinFET devices and gate-all-around (GAA) FET devices, which involve advanced fabrication techniques such as epitaxy, chemical mechanical polishing, and atomic layer deposition, to create multi-gate transistors with improved carrier mobility and chip area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down to increase functional density, then production efficiency and cost are improved, but processing and manufacturing complexity increases
Solution Approach 1:
The gate dielectric layer is segmented into different thickness regions: a first thickness over the fin top surface and a second thickness over the mandrel structure. This segmentation allows optimized electrical performance over the active channel while maintaining manufacturability through selective deposition processes
Solution Approach 2:
The gate dielectric exhibits local quality variations with different thicknesses at different locations: thicker over the fin top for optimal gate control, and thinner over the mandrel for process control. This local differentiation resolves the contradiction by tailoring properties to specific functional requirements
2Reliability
If advanced transistor structures like FinFET and GAA FET are developed, then carrier mobility and device performance are improved, but manufacturing complexity increases
Solution Approach 1:
A mandrel structure is formed beforehand to serve as a template for selective gate dielectric deposition. This preliminary action enables precise thickness control during subsequent deposition processes, facilitating advanced transistor structures with improved performance while managing manufacturing complexity
Solution Approach 2:
The mandrel structure acts as an intermediary element that enables selective deposition of the gate dielectric layer. It mediates between the deposition process and the final device structure, allowing precise thickness control without requiring complex in-situ measurement and adjustment systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These advanced transistor structures enhance carrier mobility, improve device performance, and facilitate more efficient manufacturing processes, addressing the complexity and scaling challenges in the semiconductor industry.
Implementation Method 1
a gate dielectric layer is deposited over the fin structure and the mandrel structure. In one embodiment, the gate dielectric layer is deposited using atomic layer deposition
Data Source
AI summary
A semiconductor device includes a channel structure, source region, a drain region, metal gate structure, and a self-assembled layer. The source region and the drain region are on opposite sides of the channel structure. A bottom surface of the source region is lower than a bottom surface of the channel structure, and a top surface of the source region is higher than a top surface of the channel structure. The metal gate structure covers the channel structure and between the source region and the drain region. The self-assembled layer is between the source region and the metal gate structure. The self-assembled layer is in contact with the bottom surface of the channel structure but spaced apart from the top surface of the channel structure.