Selective Gate Spacers via Blocking Material Chemistry
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Solution Overview
Problem
Current integrated processes for forming tri-gate transistor devices are complex, costly, and prone to damage and defects due to non-selective deposition of dielectric gate spacers, requiring multi-step processes that complicate the fabrication of desired structures.
Innovation Solution
A blocking material with different surface chemistry than the gate is formed on a semiconductor fin, allowing for a conformal layer to be selectively deposited on the gate while avoiding unwanted regions, using techniques such as self-assembled monolayers and etch selectivity to simplify the process and reduce damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If non-selective deposition is used to form dielectric gate spacer material, then the material is formed over desired regions (sacrificial gate), but the material is also formed over undesired regions (source and drain contact regions of the fin)
Solution Approach 1:
A blocking material is deposited on the fin before the gate spacer material deposition. This preliminary action creates selective regions that prevent dielectric material formation on undesired areas, enabling precise control of gate spacer placement without requiring multiple subsequent process steps to correct non-selective deposition.
Solution Approach 2:
The blocking material acts as an intermediary layer between the fin and the gate spacer material. This intermediate layer selectively prevents the deposition of dielectric gate spacer material on specific regions (source and drain contact regions), thereby achieving the desired selectivity without complicating the overall process.
2Manufacturing precision
If multi-step process is used to form gate spacers, then desired gate spacer structures can be formed, but the process becomes complicated and costly
Solution Approach 1:
The blocking material is deposited in advance on the fin structure before gate spacer formation. This preliminary preparation enables a simplified single-step deposition process for the gate spacer material, eliminating the need for complex multi-step processes while maintaining high structural accuracy.
Solution Approach 2:
The fin structure is segmented into desired and undesired regions through selective blocking material deposition. This segmentation allows the gate spacer material to be deposited uniformly in a single step while automatically forming only on desired regions, simplifying the manufacturing process without compromising precision.
3Manufacturing precision
If multi-step process is used for gate spacer formation, then gate spacers can be formed, but damage to the fin (channel region and source/drain region) occurs
Solution Approach 1:
The blocking material is deposited beforehand on the fin to protect undesired regions. This preliminary protective layer prevents damage to the channel and source/drain regions during gate spacer formation, eliminating the need for repeated processing steps that would otherwise cause cumulative damage to the fin structure.
4Manufacturing precision
If multi-step process is used for gate spacer formation, then gate spacers can be formed, but defect levels increase
Solution Approach 1:
The blocking material is deposited in advance to define precise deposition regions. This preliminary structuring ensures that gate spacer material is deposited only where intended in a single controlled step, minimizing defects that would otherwise arise from multiple processing cycles and improving overall device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces costs, and enhances the quality of tri-gate transistor devices by eliminating unnecessary steps and minimizing damage to the semiconductor fin, leading to improved performance and manufacturing yields.
Implementation Method 1
A blocking material with different surface chemistry than the gate is formed on a semiconductor fin, allowing for a conformal layer to be selectively deposited on the gate while avoiding unwanted regions
Implementation Method 2
using techniques such as self-assembled monolayers and etch selectivity to simplify the process and reduce damage
Data Source
AI summary
Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.